Cypress FM4 Series - Page 801

CHAPTER 14: External Bus Interface
FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E 801
 Setup procedure example of SDRAM refresh count bit
Notes:
− For the details of APB2 Prescaler Register, see 5.6. APB2 Prescaler Register of Chapter Clock.
− TYPE3-M4, TYPE4-M4, TYPE5-M4, TYPE6-M4 products don’t have to setup the above.
Refresh count setup start
Operating SDRAM?
Set REFC bit of Refresh Timer Register
(REFTIM).
Is the division ratio of
MSDCLK 1/2 ~ 1/8?
End of setup
Yes
No
Set APBC2 bit of APB2 Prescaler Register
(APBC2_PSR) so that the frequency of PCLK2
becomes later than the frequency of MSDCLK
No
Yes
REFC bit cannot set.
Stop SDRAM operation before REFC bit set.
Use clock division?
Yes
No