Cypress FM4 Series - Page 802

CHAPTER 14: External Bus Interface
802 FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E
 Setup procedure example of SDRAM command register
Notes:
− For the details of APB2 Prescaler Register, see 5.6. APB2 Prescaler Register of Chapter Clock.
− TYPE3-M4, TYPE4-M4, TYPE5-M4, TYPE6-M4 products don’t have to setup the above.
SDRAM command setup start
Use clock division?
Set SDRAM Command register (SDRAM)
Is the division ratio of
MSDCLK 1/2 to 1/8?
End of setup
Yes
No
Set APBC2 bit of APB2 Prescaler Register
(APBC2_PSR) so that the frequency of PCLK2
becomes later than the frequency of MSDCLK
Yes
SDRAM Command Register (SDCMD)
cannot set.
Stop SDRAM and set the division ratio of
MSDCLK 1/1 to 1/8.
No