Cypress FM4 Series - Low-Speed CR Prescaler Configuration

CHAPTER 2-4: Low-Speed CR Prescaler
FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E 133
2. Low-speed CR Prescaler Configuration
This section shows the block diagram of low-speed CR prescaler.
Block Diagram of Low-speed CR Prescaler
For the block diagram of low-speed CR prescaler, see Figure 2-1.
Figure 2-1 Block Diagram of Low-speed CR Prescaler
 Low-speed CR Prescaler Load Register (LCR_PRSLD)
Sets the division ratio (reload value) of Low-speed CR Prescaler.
 Low-speed CR Reload Counter
This is the down counter which generates the Low-speed CR Division Clock (CLKLC).
Low-speed CR prescaler
CLKLC
Low-speed
CR Clock
BUS
bit5
bit4
bit3
bit2
bit1
bit0
Low-speed CR
Reload Counter
Underflow
＞
Reload register (LCR_PRSLD)