Cypress FM4 Series - Dreqenb[N] Register

CHAPTER 11: DSTC
FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E 567
5.8 DREQENB[n] Register
The DREQENB[n] Register determines whether HW channel n is used.
Register configuration
Address
0x10
Field
DREQENB[31:0]
+0x14
Field
DREQENB[63:32]
+0x18
Field
DREQENB[95:64]
+0x1C
Field
DREQENB[127:96]
+0x20
Field
DREQENB[159:128]
+0x24
Field
DREQENB[191:160]
+0x28
Field
DREQENB[223:192]
+0x2C
Field
DREQENB[255:224]
Attribute
(applicable to all areas)
R/W
Initial value
(applicable to all areas)
0x00000000
Register function
The DREQENB[n] (DMA request enable) Register determines whether HW channel n is used in the initial
settings. When the DSTC is in the normal state, write access can be made to this register.
Write "1" to the DREQENB[n] Register to use HW channel n. Write "0" to the DREQENB[n] Register to
not use HW channel n. If the DREQENB[n] Register is "0", the interrupt signal or transfer request signal
(DREQ[n]) of a peripheral connected to the DSTC is ignored. The value of the DREQENB[n] Register
cannot be modified by the DSTC.
In case that the peripheral interrupts are shared with transfer request to DSTC, the value of the
DREQENB[n] Register determines which of the interrupt signal from a peripheral and HWINT[n] from the
DSTC is selected as an interrupt signal connected to the NVIC. For its details, see
"2 DSTC Operations Overview and DSTC System Configuration".
bit[255:0] DREQENB[255:0] (DMA request enable)
Access
Function
Writing "0"
Disables the DREQ signal from the peripheral. (Initial value)
Writing "1"
Enables the DREQ signal from the peripheral.
Reading
A read access to these bits reads the value of these bits.
If the DSTC installed in a product supports HW-128 channels, the DREQENB[255:128] bits are a
reserved area whose value is fixed at "0".
If the DSTC installed in a product supports HW-64 channels, the DREQENB[255:64] bits are a reserved
area whose value is fixed at "0".