Cypress FM4 Series - Peripheral Clock Control Register 1 (CKEN1)

CHAPTER 2-2: Clock Gating
FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E 97
4.3 Peripheral Clock Control Register 1 (CKEN1)
This section explains the peripheral clock control register 1 (CKEN1).
bit
31
30
29
28
27
26
25
24
Field
Reserved
Attribute
-
Initial value
-
bit
23
22
21
20
19
18
17
16
Field
Reserved
QDUCK[3:0]
Attribute
-
R/W
Initial value
-
1111
bit
15
14
13
12
11
10
9
8
Field
Reserved
MFTCK[3:0]
Attribute
-
R/W
Initial value
-
1111
bit
7
6
5
4
3
2
1
0
Field
Reserved
BTMCK[3:0]
Attribute
-
R/W
Initial value
-
1111
[bit31:20] Reserved: Reserved bits
Write 0 to these bits.
[bit19:16] QDUCK[3:0]: Settings for operation clock supply and gating of quad counter
These bits control the operation clock supply and gating of quad counter. The correspondence between
each bit and quad counter is shown below.
bit16 - QDUCK0: Quad counter unit 0
bit17 - QDUCK1: Quad counter unit 1
bit18 - QDUCK2: Quad counter unit 2
bit19 - QDUCK3: Quad counter unit 3
When the relevant bit is set to 1, the bus clock is supplied to the unit of the corresponding quad counter to
use the quad counter function. For products to which the relevant quad counter unit is not mounted, do
not change the relevant bit from the initial value.
When the relevant bit is set to 0, the bus clock input to corresponding quad counter is stopped. While the
bus clock input is gated, the quad counter of the relevant unit cannot be used.
bit
Description
0
Gates the bus clock input to the corresponding quad counter.
1
Supplies the bus clock to the quad counter corresponding to the relevant bit. (Initial value)
[bit15:12] Reserved: Reserved bits
Write 0 to these bits.