Cypress FM4 Series - Major Changes

C. Major Changes
FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E 1097
1. Major Changes
Spansion Publication Number: MN709-00001
Page
Section
Changes
Revision 1.0
-
-
Initial release
Revision 2.0
7 to 8
The target products in this manual
Added TYPE1-M4, TYPE2-M4, TYPE3-M4.
24
CHAPTER 1:System Overview
1.1 Bus Block Diagram
Corrected Figure 1-1.
26
1.3 Memory Map
Corrected Figure 1-2.
27 to 29
1.4 Peripheral Address Map
Corrected Table 1-1.
30 to 32
2. M4F Architecture
Added HTM, ETB.
36
CHAPTER 2-1: Clock
1. Overview
Added I2S clock.
40
2. Clock Generation Unit
Configuration/Block Diagram
Added I2S clock.
43
3.3 PLL clock control
Added Example of PLL multiplication ratio settings in Table 3-1.
47
4. Clock Setup Procedure Examples
Added the explanation in Note of Figure 4-2.
71
6. Clock Generation Unit Usage
Precautions
Corrected the explanation in "Correlation between the clock mode switching
and the oscillation stable bit".
73 to 104
CHAPTER 2-2: Clock Gating
Added "Programmable CRC", "I2S Interface", "HDMI-CEC/Remote Control
Reception", and "Hi-Speed Quad SPI controller".
76
1. Peripheral Clock Gating Overview
Added the explanation in Remarks of Table 1-1.
91
4.3 Peripheral Clock Control Register 1
(CKEN1)
Corrected the explanation for MFTCK[3:0].
111
CHAPTER 2-3: High-Speed CR
Trimming
4.High-Speed CR Trimming Function
Setup Procedure Example
Corrected the explanation for main clock to CLKMO.
113
4. High-Speed CR Trimming Function
Setup Procedure Example
Corrected Figure 4-4.
149
CHAPTER 3:Clock supervisor
7. Usage Precautions
Added the explanation for reset issue of Main Timer mode.
Added the explanation for "The settings for CSV OFF and external reset".
170
CHAPTER 5:Low-voltage Detection
3. Explanation of Operations
Corrected the figure of Operations of Low-Voltage Detection Reset Circuit .
Added Note.
175
5.1 Low-voltage Detection Voltage
Control Register (LVD_CTL)
Revised the description to each TYPE.
194 to 196
CHAPTER 6: Low Power Consumption
Mode
3.Operations in Standby Modes
Corrected Table 3-1, Table 3-2, Table 3-3, and Table 3-4.
200
3.2 Operations in TIMER Modes
Added HDMI-CEC reception interrupt in return factor from timer mode.
202
3.3 Operations in RTC Mode
Added HDMI-CEC reception interrupt in return factor from RTC mode.
214
5.1 Operations in Deep Standby RTC
Mode
Added the explanation in Notes.
216
5.2 Operations in Deep Standby Stop
Mode
Added the explanation in Notes.
223
8.2 Sub Clock Supply Control Register
(RCK_CTL)
Deleted RTCCKE bit.
Added CECCKE bit.
225
8.4 Deep Standby Return Factor
Register 1 (WRFSR)
Added the explanation in Notes.
226
8.4 Deep Standby Return Factor
Register 2 (WIFSR)
Added the explanation in Notes.
233 to 234
CHAPTER 7-1:VBAT domain
Configuration
Added new content
235 to 288
CHAPTER 7-2:VBAT Domain(A)
Corrected the erratum based on Rev. 1.0 CHAPTER7: VBAT domain
corresponding "TYPE1-M4 to TYPE2-M4".