Cypress FM4 Series - Page 1098

C. Major Changes
1098 FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E
Page
Section
Changes
289 to 342
CHAPTER 7-3:VBAT Domain (B)
Added new Chapter for TYPE3-M4.
343 to 412
CHAPTER 8: Interrupts
Added the explanation corresponding to "TYPE3-M4".
Corrected the explanation and erratum.
418
CHAPTER 9:External Interrupt and NMI
Control
Sections
3.2 Operations of NMI control section
Added the explanation and Note.
426
4.6 Non Maskable Interrupt Factor
Register (NMIRR)
Added Note.
433
CHAPTER 10: DMAC
2.1 DMAC and System Configuration
Added the condition asserted by MFS's transfer stop request signal.
479 to 554
CHAPTER 11: DSTC
Added the explanation corresponding to "TYPE3-M4".
Corrected the erratum.
555 to 692
CHAPTER 12: I/O Port
Added the explanation corresponding to "TYPE3-M4".
Corrected the erratum.
700
CHAPTER 13: CRC
2.2 CRC use examples
Corrected the erratum in f use example 4.
698 to 700
2.2 CRC use examples
Corrected Figure2-2, 2-3, 2-4, 2-5.
707 to 792
CHAPTER 14: External Bus Interface
Added the explanation corresponding to "TYPE3-M4".
Corrected the erratum.
866
CHAPTER 15: SD Card Interface
5. SDCLK
Added the new content.
867 to 874
CHAPTER 16:Debug Interface
Added the explanation corresponding to "TYPE3-M4".
Corrected the erratum.
883 to 906
CHAPTER 19:Programmable CRC
Added new Chapter.
-
-
Company name and layout design change
Revision 3.0
5
Peripheral Manual
Added "GDC Part"
9
The target products in this manual
Added TYPE4-M4
22
CHAPTER1:System Overview
1. Bus Architecture
Added GDC
24
CHAPTER1: System Overview
1.1 Bus Block Diagram
Revised Figure 1-1 Bus Block Diagram
26
CHAPTER1: System Overview
1.3 Memory Map
Revised Figure 1-2 Memory Map
Added Note
27 to 29
CHAPTER1: System Overview
1.4 Peripheral Address Map
Revised Table 1-1 Peripheral Address Map
36, 39, 40,
71
CHAPTER2-1:Clock
Added GDC clock
Revised Figure 2 1 Block Diagram of Clock Generation Unit
75
CHAPTER2-2:Clock Gating
Revised the following description:
Clock Generation Unit *4 → Reset Generation Unit *4
97, 100
CHAPTER2-2:Clock Gating
Added TYPE4-M4
153
CHAPTER4:Resets
2. Configuration
Added "CSV reset" and "FCS reset"
155, 156
CHAPTER4:Resets
3.1 Reset Factors
Corrected Software Watchdog Reset (SWDGR)
Corrected Anomalous Frequency Detection Reset (FCSR)
162
CHAPTER4:Resets
4. Determining operation mode
Revised the following description:
The operation mode is determined as PONR
→The operation mode defined by MD0 and MD1 is determined as PONR
175
CHAPTER5: Low-voltage Detection
5.1 LVD_CTL
Added TYPE4-M4
Corrected SVHI table
194 to 196,
200
CHAPTER6: Low Power Consumption
Mode
3. Operations in Standby Modes
Added "GDC "
Revised Table 3-1 Clock operation states in SLEEP mode
Revised Table 3-2 Clock operation states in TIMER mode
Revised Table 3-3 Clock operation states in RTC mode and STOP mode
Revised Table 3-4 Factors for returning from standby mode
211
CHAPTER6: Low Power Consumption
Mode
5. Operations in Deep Standby Modes
Revised Table 5-1 Clock operation states in deep standby mode