C. Major Changes
FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E 1099
CHAPTER7-1:VBAT domain
Configuration
CHAPTER7-3: VBAT Domain(B)
CHAPTER8:Interrupts
1. Overview
Added the following description:
Each bit of IRQxxxMON register in the case of non-equipped in each product, is
a reserved bit
CHAPTER8:Interrupts
2. Lists of Interrupts
Added Table 2-2 List of exception sources and interrupt sources
Added Table 2-5 List of interrupt signals input to DSTC
CHAPTER8:Interrupts
3.2 Relocate Interrupt Selection Register
Revised SELBIT[7:0] → SELBIT[15:0]
382, 390,
394, 396,
398, 400,
411, 413,
414, 417
CHAPTER8:Interrupts
3. Registers
Added "GDCINT",
"GSDRAM","GPLLINT","GQSPIDINT","I2S1DINT","I2S1INT",
CHAPTER11:DSTC
2.2 DSTC and system configuration
CHAPTER11:DSTC
3.1.5 Other DES settings
Revised the following description:
3.3.2 HW Transfer flow → 3.2.4 Control of HW Transfer
Revised Table 2-4 Fixed Priority of EPFR
Revised Table 4-1 Register List of the I/O Port
CHAPTER12:I/O Port
4.7 Extended Pin Function Setting
Register
Added EPFR27, EPFR28, EPFR29, EPFR30
CHAPTER12:I/O Port
4.8 EPFR00
CHAPTER12:I/O Port
4.9 EPFR01
Revised the following description:
Uses the internal macro pin CRTRIM for input of the input capture IC03.
→Setting is prohibited.
CHAPTER12:I/O Port
4.24 EPFR16
CHAPTER12:I/O Port
4.31 EPFR23
CHAPTER12:I/O Port
4.32 EPFR24
CHAPTER12:I/O Port
4.34 EPFR26
CHAPTER12:I/O Port
4.35 EPFR27
4.36 EPFR28
4.37 EPFR29
4.38 EPFR30
CHAPTER12:I/O Port
4.41 PDSRx
745, 776,
785, 786,
791, 811
CHAPTER14: External Bus Interface
CHAPTER16: Debug Interface
The target products in this manual
Table4 TYPE4-M4 Product list
Revised TYPE4-M4 Product list
CHAPTER 1: System Overview
1.3 Memory Map
1.4 Peripheral Address Map
Added MFSI2S and Smartcard
CHAPTER 2-1: Clock
3.6 Clock Gear Function
5.17 PLL Clock Gear Control Register
(PLLCG_CTL)
Added Clock Gear Function
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