Cypress FM4 Series - Page 1100

C. Major Changes
1100 FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E
Page
Section
Changes
84,
104, 105,
108, 109
CHAPTER 2-2: Clock Gating
1.Peripheral Clock Gating Overview
4.5 Peripheral Clock Control
Register2(CKEN2)
4.6 Peripheral Function Reset Control
Reset2(MRST2)
Added MFSI2S interface and Smartcard in Table 1-1
Added IISCCK[1:0] and ICCCK[1:0]
Added IISCRST[1:0] and ICCRST[1:0]
185
CHAPTER 5: Low-voltage Detection
5.1 Low-voltage Detection Voltage
Control Register(LVD_CTL)
Added TYPE5-M4 and TYPE6-M4
233
CHAPTER 6: Low Power Consumption
Mode
8.2 Sub Clock Supply Control
Register(RCK_CTL)
Added RTCCKE bit (TYPE5-M4)
255, 309
CHAPTER 7-3: VBAT domain(A) (B)
2.1 Interfacing with Always -on Domain
Added detail explanation of WTCR10 register.
246
CHAPTER 7-1: VBAT domain
Configuration
1.Configuration
Added TYPE5-M4 and TYPE6-M4
287
CHAPTER 7-3: VBAT domain(B)
7.Registers
7.3 CCS/CCB Resister
Revised CCS/CCB registers of TYPE4-M4.
361 to 368
429
CHAPTER 8: Interrupts
2. Lists of Interrupts
3.36 IRQ117 Batch Read
Register(IRQ117MON)
Added TYPE5-M4 and TYPE6-M4 in Table 2-1
Added ICC1INT and ICC0INT in IRQ117 bit4,3
440, 454
CHAPTER 9: External Interrupt and NMI
Control Sections
1.Overview
4.8 External Interrupt Factor Level
Register 2 (ELVR2)
Added both rising and falling edges in TYPE5-M4 and TYPE6-M4
Added ELVR2 register of both rising and falling edges setting
589,
728 to 731
CHAPTER 12: I/O port
2.Configuration, Block Diagram, and
Operation
4.39
Added MFS-I2S and Smartcard in Table 2-4
Added EPFR33 register of setting Smartcard interface
757 to 842
CHAPTER 14: External Bus Interface
Added TYPE5-M4 and TYPE6-M4
916
CHAPTER 15: SD Card Interface
5.SDCLK
Added TYPE5-M4 and TYPE6-M4
921
CHAPTER 16: Debug Interface
2.2 Trace Pins
Added TYPE5-M4 and TYPE6-M4
1094
Appendixes
A. Register Map
1. Register Map
Corrected Base Address of GDC Sub System SDRAM Controller
NOTE: Please see “Document Revision History” about later revised information.