Cypress FM4 Series - Auto Block Erase Access

CHAPTER 14: External Bus Interface
772 FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E
3.3.3 Auto Block Erase Access
Figure 3-8 shows the flowchart of the auto block erase access.
Figure 3-8 Auto Block Erase Access
As shown in the above flowchart, access to another memory device is possible even in the stage where
the process of accessing NAND Flash memory has not finished. Because reading or writing data can be
substituted by DMA, the processor can access the NAND Flash memory with minimum operations.

Accesses to other devices (SRAM) are available during
this period (a few s)
Issue an auto block erase setting command
0x60  (Base+0x1000)
Issue an address  (Base+0x2000)
Issue an erase start command
0xd0  (Base+0x1000)
Turn NAND mode ON

The corresponding chip select signal is fixed to "L".
Status read  (Base+0x0000)
Status = OK?
Issue a status read command
0x70  (Base+0x1000)

MNCLE is asserted/de-asserted.

MNALE is asserted.

MNALE is de-asserted.
End auto block erase
No
Yes