Cypress FM4 Series - HW Transfer Flow

CHAPTER 11: DSTC
534 FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E
3.3.2 HW Transfer Flow
The operations the DSTC executes after receiving an HW Start Trigger from a peripheral are explained
below. Figure 3-9 shows a flow chart of the operations of the DSTC. Numbers in the figure correspond to
those used in the explanation after the figure.
Figure 3-9 DSTC Operation Flow (HW Transfer)
#1 Start HW[0] transfer
(DREQ[0] asserted from peripheral)
#3 Select HW transfer channel [n] by Arbiter1
#1 Start HW[1] transfer
(DREQ[1] asserted from peripheral)
#1 Start HW[255] transfer
(DREQ[255] asserted from peripheral)
* * *
#2
(DREQENB[0]==1)
&& (DQMSK[0]==0)
&&(MONERS:ESTOP==0)?
#4
HWDESPBUF <= HWDESP[n] reg.
(if need )
Y
N
Y Y
* * *
#5
Running SW transfer?
Y
#10
SW transfer
error?
#6
HW priority > SW priority?
by CFG:SWPR
#7
Is there SW
transfer request?
N Y
Y N
N
Y
#13
(CFG:ESTE==0)?
N
#9 Waiting until SW
transfer chaining timing
#18 Update DESP for chain
HWDESPBUF <= next
#12
SW transfer
chain lock?
Y N
#22
(CFG:ESTE==0)?
Y
N
#11
SW transfer
chain?
N
Y
N
(A)
Y
#20 HWINT[n] <=1
Y
#15
MONERS <= SW error information
SWTR:SWREQ <=0
MONERS:ESTOP <=1
#14
MONERS <= SW error information
SWTR:SWREQ <= 0
#23
MONERS <= HW[n] error information
DQMSK[n] <= 1
#8 Start next SW transfer
(A)
#25
HW[n] transfer error end
(Wait next trigger)
#24
MONERS <= HW[n] error information
DQMSK[n] <= 1
MONERS:ESTOP <= 1
#16
(MONERS:ESTOP==1)?
(A)
N
#17
Data transfer by
DES@HWDESPBUF
(A)
Please see Figure 3-10.
Transfer normal end
without I.F. set
Chain start trigger
#19
(CHLK==1)?
N
Branch
Transfer error end
Out of Infinity loop end
Transfer normal end
with I.F. set
#21
HW[n] transfer normal end
(Wait next trigger)
#2
(DREQENB[1]==1)
&& (DQMSK[1]==0)
&&(MONERS.ESTOP==0)?
N
#2
(DREQENB[255]==1)
&& (DQMSK[255]==0)
&&(MONERS:ESTOP==0)?
N
(B)
(B)
Y
(C)
(C)