CHAPTER 11: DSTC
FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E 535
#1 The DSTC starts the HW Transfer from the assertion of the DREQ[n] signal from a peripheral.
#2 If the DREQENB[n] Register, the DQMSK[n] Register and the MONERS Register are
(DREQENB[n]==1)&& (DQMSK[n]==0) &&(MONERS:ESTOP==0), the DSTC proceeds to #3. If the
DQMSK[n] Register or ESTOP Register is set to 1, the DSTC ignores the DREQ[n] signal from a
peripheral and holds the start of the HW Transfer.
#3 Processes in #3 are processes to be executed by Arbiter 1. In the case of transfer requests from
multiple HW channels. the DSTC selects the number of the HW channel (n) on which it executes a
transfer. The DSTC keeps the transfer requests from other channels until the transfer on the HW[n]
selected ends normally or ends due to an error and the DSTC starts waiting for a Start Trigger.
#4 Based on the channel number (n) selected, store the DESP value of the HWDESP[n] Register in
HWDESPBUF. If the channel number is the same as the one in the previous reference, and the value
of HWDESPBUF is valid, it is skipped to refer to the HWDESP[n] Register.
Processes explained in #5 to #16 are details of operations of Arbiter 2 and processes in other SW
Transfer. The DSTC executes the same processes as #4 to #15 in SW Transfer flow. If there is a SW
Start request and that SW Transfer has a high priority, or if the Chain Start in that SW Transfer has been
locked, the DSTC executes that SW Transfer first. In addition, if that SW Transfer ends in the form of error,
the DSTC records the error information of the SW Transfer in the MONERS Register. If the ESTOP bit is
set to 1 due to the error end of the SW Transfer, the DSTC holds the transfer start of HW[n].
#17 The flow inside the bold box shows the transfer operations of the DSTC according to the DES
specified in DESP. For details of the flow inside the bold box, see section Operation flow after
specifying of DESP. In the case of the HW Transfer, the DSTC executes the transfer according to the
DES specified in HWDESP. After the transfer has been processed, the operation of the DSTC
branches to one of the five operations shown in Figure 3-10.
#18 In the case of a Chain Start, the DSTC updates HWDESPBUF.
#19 If CHLK is 1, the DSTC proceeds to #17 and successively executes the transfers started by the
Chain Start. Otherwise the DSTC proceeds to #6.
#20 If the transfer ends normally and there is an interrupt flag set instruction, the DSTC sets HWINT[n] to 1.
#21 The DSTC ends the transfer caused by the HW Start trigger in #1. The DSTC waits for either a new
Start Trigger or a succeeding Start Trigger. If the DSTC keeps the HW Start Trigger for other channel in
#3, Arbiter 1 selects the channel on which a transfer is to be executed and the DSTC proceeds to #4.
#22 If that HW Start transfer has ended in the form of error and CFG:ESTE is 0, the DSTC proceeds to #23.
Otherwise the DSTC proceeds to #24.
#23 If there has been no error record in the MONERS Register, the MONERS Register records the error
information of the DES of the HW Transfer being executed. If there is an error record, the DSTC sets
the DER bit to 1. In addition, the DSTC sets the DQMSK[n] Register to 1 to suppress future transfer
requests from HW channel n.
#24 The same process as #23 is executed. At the same time, the ESTOP bit in the MONERS Register is
set to 1, and the DSTC holds the start of other Start transfer.
#25 The transfer caused by the HW Start Trigger in #1 ends in the form of error. The HWINT[n] Register
is not set to 1 regardless of the value of CHRS. The DSTC waits for a new Start Trigger. If the DSTC
keeps the HW Start Trigger for other channel, Arbiter 1 selects the channel on which a transfer is to be
executed and the DSTC proceeds to #4.
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