Cypress FM4 Series - Software Watchdog Clock Prescaler Register (SWC_PSR)

CHAPTER 2-1: Clock
66 FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E
5.7 Software Watchdog Clock Prescaler Register (SWC_PSR)
The SWC_PSR sets the frequency division and enables the output of the software watchdog clock.
Register configuration
bit
7
6
5
4
3
2
1
0
Field
Reserved
SWDS
Attribute
-
R/W
Initial value
-
00
Register functions
[bit7:2] Reserved: Reserved bits
0b000000 is read from these bits.
Set these bits to 0b000000 when writing.
[bit1:0] SWDS: Software watchdog clock frequency division ratio setting bits
bit1
bit0
Description
0
0
Sets 1/1 frequency of PCLK0. [Initial value]
0
1
Sets 1/2 frequency of PCLK0.
1
0
Sets 1/4 frequency of PCLK0.
1
1
Sets 1/8 frequency of PCLK0.
Note:
− This register is not initialized by software reset.