CHAPTER 15: SD Card Interface
850 FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E
2.6 Command Register
The Host Driver shall check the Command Inhibit (DAT) bit and Command Inhibit (CMD) bit in the Present
State Register before writing to this register. Writing to the upper byte of this register triggers SD
command generation. The Host Driver has the responsibility to write this register because the Host
Controller does not protect for writing when the Command Inhibit (CMD) bit is set to 1.
*: If an Asynchronous Abort is executed while a data transfer for which Auto CMD12 Enable is selected
in the Auto CMD Enable bit in the Transfer Mode Register is in progress, the operation of this macro is
explained below.
− If the macro recognizes the trigger of the Asynchronous Abort before issuing the Auto CMD12, it
issues an Abort Command using the Asynchronous Abort. After having received the response to
the Abort Command, the macro sets the Command Complete bit in the Normal Interrupt Status
Register.
− The macro ignores the trigger of the Asynchronous Abort while issuing Auto CMD12. As the Abort
Command is an Auto Abort Command, the macro does not set the Command Complete bit in the
Normal Interrupt Status Register to 1 even after having received the response to the Abort
Command. In this situation, the completion of issuing the Abort Command is confirmed if the
Transfer Complete bit in the Normal Interrupt Status Register is set to 1. Therefore, continue a
data transfer until one of the conditions for setting the Transfer Complete bit is met.
Moreover, if one of the situations mentioned above occurs, execute the software reset in the
Asynchronous Abort sequence after having issued the Abort Command.
For other details of this register, refer to SD Specifications Part A2.
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