Cypress FM4 Series - Shared Bus Control Register

CHAPTER 15: SD Card Interface
FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E 881
2.32 Shared Bus Control Register
The devices on a shared bus are not intended to be controlled by the Standard Host Driver.
D31
D30 D24
D23
D22 D20
D19
D18 D16
D15
D14 D08
D07 D06
D05 D04
D03
D02 D00
Rsvd
Back-End Power Control
Rsvd
Interrupt Pin Select
Rsvd
Clock Pin Select
Rsvd
Bus Width Preset
Rsvd
Number of
Interrupt Input
Pins
Rsvd
Number of Clock Pins
Bit
Attribute
Description
31
Rsvd
Reserved
30-24
RW
Back-End Power Control
Each bit in this field controls the back-end power supply of an embedded device.
Settings:
0: The back-end power is off.
1: The back-end power is supplied.
Set/Reset
Condition
Set
1 Write
Reset (0)
System reset
Software Reset For All
0 Write
23
Rsvd
Reserved
22-20
RW
Interrupt Pin Select
This field enables interrupt pin inputs.
Settings:
0b000: An interrupt is detected by the interrupt cycle.
0bxx1: INT_A is enabled.
0bx1x: INT_B is enabled.
0b1xx: INT_C is enabled.
Set/Reset
Condition
Set
1 Write
Reset (0)
System reset
Software Reset For All
0 Write
19
Rsvd
Reserved