Cypress FM4 Series - Extended Pin Function Setting Register 26 (EPFR26)

CHAPTER 12: I/O Port
FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E 709
4.34 Extended Pin Function Setting Register 26 (EPFR26)
The EPFR26 register assigns functions of Hi-Speed SPI controller.
Register Configuration
bit
31
30
29
28
27
26
25
24
Field
Reserved
Attribute
-
Initial value
-
bit
23
22
21
20
19
18
17
16
Field
Reserved
Q_IO3B
Attribute
-
R/W
Initial value
-
00
bit
15
14
13
12
11
10
9
8
Field
Q_IO2B
Q_IO1B
Q_IO0B
Q_IO3E
Attribute
R/W
R/W
R/W
R/W
Initial value
00
00
00
00
bit
7
6
5
4
3
2
1
0
Field
Q_IO2E
Q_IO1E
Q_IO0E
Q_SCKB
Attribute
R/W
R/W
R/W
R/W
Initial value
00
00
00
00
Register Function
[bit31:18] Reserved: Reserved bits
0x0000 is read from these bits.
When writing these bits, set them to 0x0000.
[bit17:16] Q_IO3B: Q_IO3 (GE_SPDQ3) Input/Output Select bits
Selects input/output for Q_IO3. TYPE4-M4 products signal in parentheses are eligible.
bit
Description
Reading
Reads out the register value.
Writing
00
Does not produce input/output of Hi-Speed SPI controller Q_IO3. [Initial value]
01
Uses Q_IO3_0 at the input/output pin of Hi-Speed SPI controller Q_IO3.
10
Setting is prohibited.
11
Setting is prohibited.
[bit15:14] Q_IO2B: Q_IO2 (GE_SPDQ2) Input/Output Select bits
Selects input/output for Q_IO2. TYPE4-M4 products signal in parentheses are eligible.
bit
Description
Reading
Reads out the register value.
Writing
00
Does not produce input/output of Hi-Speed SPI controller Q_IO2. [Initial value]
01
Uses Q_IO2_0 at the input/output pin of Hi-Speed SPI controller Q_IO2.
10
Setting is prohibited.
11
Setting is prohibited.