Cypress FM4 Series - Slot Interrupt Status Register

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CHAPTER 15: SD Card Interface

FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E 883

2.33 Slot Interrupt Status Register

This register indicates the logical OR of the interrupt signal and wakeup signal for each slot.

D15 D08

D07 D00

Rsvd

Interrupt Signal For Each Slot

*: Since this Family does not support multiple slots, it does not have this register.

Main Page

Default Chapter10
- Table of Contents10
CHAPTER 1: System Overview23
- Bus Architecture24
- Cortex-M4F Architecture32
  - Option Configuration35
- Mode36
CHAPTER 2-1: Clock37
- Clock Generation Unit Overview38
- Clock Generation Unit Configuration/Block Diagram39
- Clock Generation Unit Operations44
- Clock Setup Procedure Examples52
- List of Clock Generation Unit Registers58
- Clock Generation Unit Usage Precautions79
- CHAPTER 2-2: Peripheral Clock Gating81
- CHAPTER 2-3: High-Speed CR Trimming113
- CHAPTER 2-4: Low-Speed CR Prescaler131
CHAPTER 3: Clock Supervisor139
- Overview140
- Configurations and Block Diagrams141
- Explanation of Operations143
- Setup Procedure Examples144
- Operation Examples146
- Registers150
CHAPTER 4: Resets159
- Overview160
- Configuration161
- Explanation of Operations162
- Register172
  - Reset Factor Register (RST_STR: Reset Status Register)173
CHAPTER 5: Low-Voltage Detection175
- Overview176
- Configuration177
- Explanation of Operations178
- Setup Procedure Examples181
- Registers182
CHAPTER 6: Low Power Consumption Mode189
- Overview of Low Power Consumption Mode190
- Configuration of CPU Operation Modes195
- Operations in Standby Modes202
- Examples of Procedure for Setting Standby Mode215
- Operations in Deep Standby Modes219
  - Operations in Deep Standby RTC Mode221
  - Operations in Deep Standby Stop Mode223
- Examples of Procedure for Setting Deep Standby Mode225
- Procedure for Determining Factor for Returning from Deep Standby Mode227
- List of Low Power Consumption Mode Registers228
CHAPTER 7-1: VBAT Domain Configuration243
- Configuration244
- CHAPTER 7-2: VBAT Domain(A)245
  - Overview of VBAT Domain246
  - Configuration of VBAT Domain248
- CHAPTER 7-3: VBAT Domain(B)299
CHAPTER 8: Interrupts353
- Overview354
- Configuration354
- Lists of Interrupts358
- Registers382
CHAPTER 9: External Interrupt and NMI Control Sections437
- Overview438
- Block Diagram438
- Operations and Setting Procedure Examples439
Chapter 10: Dmac453
- Overview of DMAC454
- Configuration of DMAC455
Chapter 11: Dstc503
- Overview of DSTC504
- DSTC Operations Overview and DSTC System Configuration505
  - Operations Overview of DSTC505
  - DSTC and System Configuration507
- Functions and Operations of DSTC510
  - Settings of des511
- Examples of DSTC Operations and Control539
- Registers and Descriptors of DSTC556
CHAPTER 12: I/O Port581
- Overview582
- Configuration, Block Diagram, and Operation583
- Setup Procedure Example591
- Registers592
- Usage Precautions739
CHAPTER 13: CRC (Cyclic Redundancy Check)741
- Overview of CRC742
- CRC Operations743
  - CRC Calculation Sequence744
  - CRC Use Examples745
- CRC Registers749
CHAPTER 14: External Bus Interface755
- Overview of External Bus Interface756
- Block Diagram758
- Operations761
- Connection Examples794
- Setup Procedure Example799
- Registers803
CHAPTER 15: SD Card Interface841
- Overview of SD Card Interface842
- Registers843
- MMC Boot Operation908
  - Example of Controlling Alternative Boot Mode (Using ADMA)910
- MMC Wait IRQ912
  - Example of Controlling Wait IRQ912
- Sdclk914
CHAPTER 16: Debug Interface915
- Overview and Configuration916
- Pin Description917
CHAPTER 17: Flash Memory923
CHAPTER 18: Unique ID Register925
- Overview926
- Registers927
  - Unique ID Register 0 (UIDR0: Unique ID Register 0)928
  - Unique ID Register 1 (UIDR1: Unique ID Register 1)929
CHAPTER 19: Programmable CRC931
- Overview of the Programmable CRC932
  - Overview932
- Configuration and Operation of the Programmable CRC933
  - Configuration of the Programmable CRC933
  - Operation of the Programmable CRC934
- Methods for Controlling the Programmable CRC936
  - Control Flow for the Programmable CRC (During Input Data Transfer from CPU)936
  - Control Flow for the Programmable CRC (During Input Data DMA Transfer with DSTC)938
- Registers of the Programmable CRC940
- Example of the Programmable CRC Computing951
  - Computing Example 1951
  - Example of Computing 2953
Appendixes955
- Register Map956
  - Register Map958
  - Flash_If959
    - TYPE1-M4, TYPE2-M4 Products959
    - TYPE3-M4 Product960
- TYPE4-M4, TYPE5-M4, TYPE6-M4 Products961
- Unique ID962
- ECC Capture Address962
- Clock/Reset963
  - TYPE1-M4, TYPE2-M4 Products963
  - TYPE3-M4, TYPE4-M4, TYPE5-M4, TYPE6-M4 Products965
- Hw Wdt967
- Sw Wdt967
- Dual_Timer968
- Mft969
  - TYPE1-M4, TYPE2-M4 Products969
  - TYPE3-M4, TYPE4-M4, TYPE5-M4, TYPE6-M4 Products972
- Ppg975
- Base Timer978
- IO Selector for Base Timer979
- Qprc980
  - TYPE1-M4, TYPE2-M4, TYPE6-M4 Products980
  - TYPE3-M4, TYPE4-M4, TYPE5-M4 Products981
- Qprc Nf982
- A/DC983
- CR Trim984
- Exti985
  - TYPE1-M4, TYPE2-M4, TYPE3-M4, TYPE4-M4 Products985
  - TYPE5-M4, TYPE6-M4 Products985
- INT-Req. READ986
  - TYPE1-M4, TYPE2-M4, TYPE6-M4 Products986
  - TYPE3-M4, TYPE5-M4 Product992
  - TYPE4-M4 Product999
- D/Ac1006
- Hdmi-Cec1007
- Gpio1008
  - TYPE1-M4, TYPE2-M4, TYPE6-M4 Products1008
  - TYPE3-M4 Product1015
  - TYPE4-M4 Product1024
  - TYPE5-M4 Product1032
- Lvd1041
- Ds_Mode1041
- USB Clock1042
- Can_Prescaler1043
- Mfs1043
- Crc1045
- Watch Counter1045
- Rtc1046
  - TYPE1-M4, TYPE2-M4, TYPE3-M4, TYPE6-M4 Products1046
  - TYPE4-M4 Product1049
  - TYPE5-M4 Product1053
- Low-Speed CR Prescaler1054
- Peripheral Clock Gating1055
  - TYPE1-M1, TYPE2-M4 Products1055
  - TYPE3-M4, TYPE4-M4 Products1055
  - TYPE5-M4, TYPE6-M4 Products1056
  - B List of Notes1093
    - Notes When High-Speed CR Is Used for the Master Clock1094
  - C Major Changes1096
    - Major Changes1097
Revision History1101

Cypress FM4 Series - Slot Interrupt Status Register

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