CHAPTER 11: DSTC
FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E 529
information (EST ≠ 000), if a transfer caused by another transfer request ends due to an error, the DSTC
sets the DER (double error) bit to 1. The DER bit is a bit that indicates a double error has occurred. As for
the second error, the DSTC notifies the CPU of only its occurrence. The MONERS Register keeps only
the information of the first error, but does not keep details of the second error. Moreover, the MONERS
Register does not record any error that occurs after the second error.
With CFG:ESTE set to 1, if a transfer error occurs, the DSTC transits to the error stop state. After
transiting to the error stop state, the DSTC holds other transfer requests and no longer starts any transfer.
That the ESTOP bit in the MONERS Register is set to 1 indicates that the DSTC is in the error stop state.
If the CPU issues an ERCLR command to the CMD Register, the DSTC is released from the error stop
state and starts transfers according to transfer requests it has been keeping.
3.2.9 Standby Function
To reduce power consumption, the DSTC has a function (standby function) for stopping the internal
clocks of the DSTC to make the DSTC stop operating. The state of the DSTC can be switched by the
standby transition command and standby release command issued to the CMD Register. Figure
3-7illustrates the operations executed in the issue of the standby transition command and in the state
transition of the DSTC.
Figure 3-7 DSTC Standby State Transition Diagram
AHB Bus Reset /
* Clear all DQMSK[n] registers
* Clear all DREQENB[n] registers
Standby
state
Read:0x01
Transition
state 1
Read:0x02
Normal
State
Read:0x00
Transition
state 2
Read:0x03
Write:0x04
Go to
Write:0x08 /
* Negate SWINT interrupt signal
* Clear SWST bit in SWTR register
* Negate all HWINT[n] interrupt signals
* Clear all HWINT[n] registers
* Negate ERINT interrupt signal
* Set all DQMSK[n] registers
else
Waiting transfer end
Transfer end /
( MONERS.EST <= 011)
else
The DSTC has four states: standby state, transition state 1, normal state and transition state 2. The state
of the DSTC can be checked by reading the value of the CMD Register via the CPU.
Upon a bus reset, the initial state of the DSTC is the standby state. If the CPU issues a standby release
command (writing 0x04) to the CMD Register, the DSTC transits to the transition state 1 and then to the
normal state.
In the normal state, if the CPU issues a standby transition command (writing 0x08) to the CMD Register,
the DSTC transits to the transition state 2 to wait for a transfer to end.
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