CHAPTER 11: DSTC
528 FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E
− One of the two bits of the reserved area of DES0 is 1. (abnormal specified value)
− TW[1:0]==11 (abnormal specified value)
− CHRS[5:4]==11 (abnormal specified value)
− (CHRS[5]==0) &&(CHRS[3]==0)&&(CHRS[1]==0) &&(CHLK ==1) (abnormal Chain setting)
− (MODE==0) && (CHRS[1:0] != 00) (abnormal setting)
− (MODE==0)&&(ORM==0x0000) && (IIN0x2000) (Out of allowed count value range in mode 0)
− (MODE==0)&&(ORM0x8000) && (IIN0x4000) (Out of allowed count value range in mode 0)
− (MODE==0)&&(ORM0x4000) && (IIN0x8000) (Out of allowed count value range in mode 0)
− (MODE==0)&&(ORM0x2000) &&(IIN==0x0000) (Out of allowed count value range in mode 0)
− (MODE==1)&&(IIN!=0x00)&&(IRM==0x00) (Out of allowed count value range in mode 1)
− (MODE==1)&&(IIN!=0x00)&&(IRM>IIN) (Out of allowed count value range in mode 1)
− (MODE==0)&&(DV[1]==1)&&(ORL[0]==0)&& (ORM != 0x0001) (abnormal counter reload setting)
− (MODE==1)&&(DV[1]==1)&&(ORL[0]==0)&& (ORM != 0x0001) (abnormal counter reload setting)
− (MODE==1)&&(DV[1]==1)&&(ORL[0]==0) && (IRM != 0x01) (abnormal counter reload setting)
− (MODE==1)&&(DV[1]==1)&&(ORL[0]==0)&& (IIN != 0x01) (abnormal counter reload setting)
− (DV[1]==1)&&(SAC[0]==0)&&(ORL[1]==0) (abnormal transfer source address reload setting)
− (DV[1]==1)&&(DAC[0]==0)&&(ORL[2]==0) (abnormal transfer destination address reload setting)
Source Access Error
If one of the following events occurs while the DSTC is accessing the transfer source address area, the
DSTC ends a transfer in the form of error end (source access error). The DSTC sets MONERS:EST to
001. At the same time, the DSTC writes 01 to DES0:ST and executes the DES close process.
− The specified transfer source start address value (SA) is unaligned to TW.
− The transfer source address value having undergone increment calculation or decrement
calculation overflows.
− The DSTC receives a bus error response from the system.
Destination Access Error
If one of the following events occurs while the DSTC is accessing the transfer destination address area,
the DSTC ends a transfer in the form of error end (destination access error). The DSTC sets
MONERS:EST to 010. At the same time, the DSTC writes 10 to DES0:ST and executes the DES close
process.
− The specified transfer destination start address value (DA) is unaligned to TW.
− The transfer destination address value having undergone increment calculation or decrement
calculation overflows.
− The DSTC receives a bus error response from the system.
Transfer Compulsory Stop Error
If the DSTC receives a standby transition command from the CPU while executing a transfer, it ends the
transfer (transfer compulsory stop error). The DSTC sets MONERS:EST to 011. At the same time, the
DSTC writes 11 to DES0:ST and executes the DES close process.
DER Function and ESTOP Function
If a transfer error occurs, the transfer of the DES that has caused the transfer error is interrupted and
ended. After the transfer has been ended, if there is a transfer start request for another DES, the setting
of the ESTE (error stop enable) bit in the CFG Register determines whether the DSTC starts the transfer
requested in the transfer start request.
In the case of CFG:ESTE = 0, if there is a new transfer request after a transfer error has occurred, the
DSTC starts the transfer for that new transfer request. The MONERS Register records error information
and keeps it until the register is cleared by the CPU. While the MONERS Register is keeping error
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