Cypress FM4 Series - SDRAM Buffer Read (TYPE3-M4, TYPE4-M4, TYPE5-M4, TYPE6-M4 Products)

CHAPTER 14: External Bus Interface
792 FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E
3.12 SDRAM Buffer Read (TYPE3-M4, TYPE4-M4, TYPE5-M4, TYPE6-M4
Products)
This function is equipped for TYPE3-M4, TYPE4-M4 products. This is not equipped for TYPE1-M4
products.
The external bus interface is equipped with built-in buffer of 5 words at most in order to improve efficiency
of serial read access to SDRAM.
In case that the BOFF bit of the SDRAM timing register (SDTIM) is 0, when read accesses occur to some
areas of SDRAM, the read data is buffered for the subsequent address.
If hitting the buffered address, the buffered data is returned. At that time, the read access to SDRAM does
not occur.
If not hitting the buffered address, the read access to SDRAM occurs. At that time, the buffered data is
cleared and the data read this time will be buffered.
In case of any of the following conditions, all buffers are cleared.
− When any read which does not hit the buffered address occurs
− When writing to SDRAM
− When the SDON bit of the SDRAM mode register (SDMODE) is set to 0
− When the BOFF bit of the SDRAM timing register (SDTIM) is set to 1
The maximum number of buffered data varies depending on the CASEL bit of the SDRAM mode register
(SDMODE), the access type and the CL bit of the SDRAM timing register (SDTIM).
Table 3-10 Maximum Number of Buffering Data
CASEL
Access Type
CL
Maximum Number of Buffering Data
0
Byte
(8 bit)
0
3 bytes
1
4 bytes
2
5 bytes
Half word
(16 bit)
0
3 half words
1
4 half words
2
5 half words
Word
(32 bit)
0
2 words
1
2.5 words
2
3 words
1
Byte
(8 bit)
0
3 bytes
1
4 bytes
2
5 bytes
Half word
(16 bit)
0
3 half words
1
4 half words
2
5 half words
Word
(32 bit)
0
3 words
1
4 words
2
5 words
Note:
− Set the CL bit of the SDRAM timing register (SDTIM) to optimal setting for your system. For
example, when 1 or 2 for CL can be set with 16-bit SDRAM, set 2 for CL in order to read serial 3
words.