Cypress FM4 Series - Page 791

CHAPTER 14: External Bus Interface
FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E 791
Write Access
To reduce the write access interval, the mode for implementing the continuous write request is provided.
If continuous access is enabled, it will improve write access efficiency because, when write access to the
external bus interface is performed continuously, it writes to the external device continuously without
waiting for an error response.
For the example of continuous write operation, see Figure 3-28. In this access, an error occurs in the 3rd
write request. But, the 4th write access is accepted without waiting for an error response. When an error
response occurs, the address of an error response factor is saved in the factor register (WEAD). The
error response is not notified to CPU.
To stop the CPU immediately after an error response from the external bus interface is received, make
the setting to disable the continuous access function with the register setting (AMODE:WAEN). However,
an interrupt due to error response can be detected in the case where the continuous access function is
enabled.
*: Condition of error response occurring
− When an access to an area where the mapping is not executed with area register is implemented
during accessing to SRAM/Flash memory address area.
− When an access to SRAM address area is implemented at SDMODE.SDON=1 during accessing to
ADRAM area.
Figure 3-28 Operation Example of Error Response Occurred in Continuous Write
Write(A)Internal bus request
Internal bus response
OK
1st time 2nd time
■Continuous Write Enabled (Operation Example)
Write(B)
Write(C)
External bus interface
(MCSX)
External bus interface
(MWE)
A
External bus interface
(MADATA)
B D
3rd time 4th time
Address(C)
External bus interface
register (EST.WERR bit)
External bus interface
register (WEAD)
External bus interface
register (error-causing
bit corresponding to
MEMCERR)
Only when
AMODE.WAEN=1 is set
■Continuous Write Disabled (Operation Example)
Write(A)
Internal bus request
retiming
(AHB → external bus)
Write(B)
Write(C)
Write(D)
WAIT OK
Write(D)
Write error
WAIT OK
Write(A)
OK
Write(B) Write(C)
A
B
Write(A)
WAIT
OKWAIT
OK
Write(B)
Write(D)
WAIT
ERROR
Write(C)
WAIT
WAIT OK
Write(D)
D
OK
1st time 2nd time 3rd time 4th time
Write error
Internal bus request
Internal bus response
External bus interface
(MCSX)
External bus interface
(MWE)
External bus interface
(MADATA)
External bus interface
register (EST.WERR bit)
External bus interface
register (WEAD)
External bus interface
register (error-causing
bit corresponding to
MEMCERR)
Internal bus request
retiming
(AHB → external bus)