Cypress FM4 Series - Extended Pin Function Setting Register 30 (EPFR30)

CHAPTER 12: I/O Port
724 FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E
4.38 Extended Pin Function Setting Register 30 (EPFR30)
EPFR30 register sets the function assignment to GDC Panel pins.
Register Configuration
bit
31
30
29
28
27
26
25
24
Field
Reserved
PNL_TSIG4E
Attribute
-
R/W
Initial value
-
00
bit
23
22
21
20
19
18
17
16
Field
PNL_TSIG3E
PNL_TSIG2E
PNL_TSIG1E
PNL_TSIG0E
Attribute
R/W
R/W
R/W
R/W
Initial value
00
00
00
00
bit
15
14
13
12
11
10
9
8
Field
Reserved
PNL_LH_SYNCE
PNL_FV_SYNCE
Attribute
-
R/W
R/W
Initial value
-
00
00
bit
7
6
5
4
3
2
1
0
Field
PNL_LEE
PNL_DENE
PNL_DCLKE
PNL_PWEE
Attribute
R/W
R/W
R/W
R/W
Initial value
00
00
00
00
Register Function
[bit31:26] Reserved: Reserved bits
0b000000 is read from these bits.
When writing these bits, set them to 0b000000.
[bit25:24] PNL_TSIG4E: PNL_TSIG4 Output Select bits
Selects output for PNL_TSIG4.
bit
Description
Reading
Reads out the register value.
Writing
00
Does not produce output of GDC Panel PNL_TSIG4. [Initial value]
01
Uses PNL_TSIG4_0 at the output pin of GDC Panel PNL_TSIG4.
10
Setting is prohibited.
11
Setting is prohibited.
[bit23:22] PNL_TSIG3E: PNL_TSIG3 Output Select bits
Selects output for PNL_TSIG3.
bit
Description
Reading
Reads out the register value.
Writing
00
Does not produce output of GDC Panel PNL_TSIG3. [Initial value]
01
Uses PNL_TSIG3_0 at the output pin of GDC Panel PNL_TSIG3.
10
Setting is prohibited.
11
Setting is prohibited.