CHAPTER 12: I/O Port
FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E 725
[bit21:20] PNL_TSIG2E: PNL_TSIG2 Output Select bits
Selects output for PNL_TSIG2.
Reads out the register value.
Does not produce output of GDC Panel PNL_TSIG2. [Initial value]
Uses PNL_TSIG2_0 at the output pin of GDC Panel PNL_TSIG2.
[bit19:18] PNL_TSIG1E: PNL_TSIG1 Output Select bits
Selects output for PNL_TSIG1.
Reads out the register value.
Does not produce output of GDC Panel PNL_TSIG1. [Initial value]
Uses PNL_TSIG1_0 at the output pin of GDC Panel PNL_TSIG1.
[bit17:16] PNL_TSIG0E: PNL_TSIG0 Output Select bits
Selects output for PNL_TSIG0.
Reads out the register value.
Does not produce output of GDC Panel PNL_TSIG0. [Initial value]
Uses PNL_TSIG0_0 at the output pin of GDC Panel PNL_TSIG0.
[bit15:12] Reserved: Reserved bits
0x0 is read from these bits.
When writing these bits, set them to 0x0.
[bit11:10] PNL_LH_SYNCE: PNL_LH_SYNC Output Select bits
Selects output for PNL_LH_SYNC.
Reads out the register value.
Does not produce output of GDC Panel PNL_LH_SYNC. [Initial value]
Uses PNL_LH_SYNC_0 at the output pin of GDC PNL_LH_SYNC.
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