Cypress FM4 Series - SRAM and nor Flash Memories Access

CHAPTER 14: External Bus Interface
FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E 767
3.2 SRAM and NOR Flash Memories Access
The following explains SRAM and NOR Flash memories access.
Memory Access
The target device for the SRAM and NOR Flash memories access will be determined with the MCSX
[7:0]/address outputs. After that, outputting MOEX/MWEX will make a read/write to the target device.
Pins Used
SRAM and NOR Flash memory accesses require the pins shown in Table 3-4.
Table 3-4 External Interface Pins used for SRAM and NOR Flash Memories
Pin Name
Function
MAD[24:0]
Address output pins
MADATA[31:0]
Data input/output pins
(These pins will be changed to input/output pins for address/data in multiplex mode.)
MCSX[7:0]
Chip select pins
MDQM[3:0]
Byte mask signal output pins
MALE
Address latch enable output pin
(Multiplex mode only)
MOEX
Output enable output pin
MWEX
Write enable output pin
MRDY
RDY signal input pin
MCLKOUT
Clock output pin
Notes:
− Not all of the pins shown in Table 3-3 will be used depending on the setups or target devices
(SRAM, or NOR Flash memory).
− Number and functions of external bus interface pins used depend on the product used. See the
data sheet of the products used for the details.