CHAPTER 14: External Bus Interface
766 FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E
Table 3-3 shows the mapping between the CPU access width and the external bus width.
Table 3-3 CPU Access Width and External Bus Width Mapping
HADDR: AHB address input
As for a target with 8-bit width, the input/output data will be determined with the values of HADDR[1:0].
As for a target with 16-bit width, the HADDR[1] is only used for data assignment.
Notes:
− General purpose ports or shared function can be selected per bit for the MAD pins and MADATA
pins. See Chapter I/O Port for the detail of the setups.
− Placement of the external bus interface pins depends on the product type. See the data sheets of
products used for the details.
To Next Page
Loading...
