Cypress FM4 Series - Page 765

CHAPTER 14: External Bus Interface
FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E 765
Bus Size Conversion and Continuous Access
If an access with an externals bus width narrower than the CPU access width is made, the access will be
divided and converted into continuous accesses which continuously change the address only with holding
MCSX="L". For example, when a 32-bit read access is made from the internal bus to the 8-bit bus width,
the address will be changed as 0 -> 1 -> 2 -> 3 with holding MCSX="L" and the data will be output
continuously from the MADATA [7:0] with the transfer timing.
The word read access waveform to the 8-bit width SRAM is shown in Figure 3-3.
The continuous word write/read access waveform to the 16-bit width SRAM is shown in Figure 3-4.
Figure 3-3 Waveform of Word Read Access to 8-bit Width SRAM
DAT00
00 01 02 03
0
*
1 2 3 4 5 6 7 8 9
10
11 12 13 14 15
16
17 18 19
*
* *
*: ON or OFF is available
MAD[24:0]
MADATA[7:0]
MOEX
MWEX
MDQM[0]
MCSX[0]
Read address setup
Read access cycle
DAT01 DAT02 DAT03
Read idle cycle
MCLK
(MCLKOUT)
Figure 3-4 Waveform of Continuous Word Write/Read Access to 16-bit Width SRAM
DAT00
00 02
00
0
*
1 2 3 4 5 6 7 8 9
10
11 12 13 14 15
16
17 18 19
*
*: ON or OFF is available
MAD[24:0]
MADATA[15:0]
MOEX
MWEX
MDQM[0]
MCSX[0]
Write address setup
DAT02 DAT00 DAT02
02
Write access cycle
Write idle cycle
Write enable cycle
MCLK
(MCLKOUT)
Note:
− The idle cycle in continuous access will be inserted only after the access to the last address.