Cypress FM4 Series - Page 723

CHAPTER 12: I/O Port
FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E 723
[bit7:6] PNL_PD19E: PNL_PD19 Output Select bits
Selects output for PNL_PD19.
bit
Description
Reading
Reads out the register value.
Writing
00
Does not produce output of GDC Panel PNL_PD19. [Initial value]
01
Uses PNL_PD19_0 at the output pin of GDC Panel PNL_PD19.
10
Setting is prohibited.
11
Setting is prohibited.
[bit5:4] PNL_PD18E: PNL_PD18 Output Select bits
Selects output for PNL_PD18.
bit
Description
Reading
Reads out the register value.
Writing
00
Does not produce output of GDC Panel PNL_PD18. [Initial value]
01
Uses PNL_PD18_0 at the output pin of GDC Panel PNL_PD18.
10
Setting is prohibited.
11
Setting is prohibited.
[bit3:2] PNL_PD17E: PNL_PD17 Output Select bits
Selects output for PNL_PD17.
bit
Description
Reading
Reads out the register value.
Writing
00
Does not produce output of GDC Panel PNL_PD17. [Initial value]
01
Uses PNL_PD17_0 at the output pin of GDC Panel PNL_PD17.
10
Setting is prohibited.
11
Setting is prohibited.
[bit1:0] PNL_PD16E: PNL_PD16 Output Select bits
Selects output for PNL_PD16.
bit
Description
Reading
Reads out the register value.
Writing
00
Does not produce output of GDC Panel PNL_PD16. [Initial value]
01
Uses PNL_PD16_0 at the output pin of GDC Panel PNL_PD16.
10
Setting is prohibited.
11
Setting is prohibited.
Notes:
− This register does not exist in TYPE1-M4, TYPE2-M4, TYPE3-M4, TYPE5-M4, TYPE6-M4
products.
− This register is not initialized by deep standby transition reset.