CHAPTER 14: External Bus Interface
FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E 793
For the operation example of SDRAM buffer read, see Figure 3-29.
Figure 3-29 Operation Example of SDRAM Buffer Read
Access conditions
− SDRAM 32-bit access
− Buffer readout OFF (SDTIM:BOFF): 0b0 (In reading, buffer for SDRAM is enabled)
− SDRAM mode (SDMODE:CASEL): 0b01 (32-bit width)
− Number of CAS latency cycles (SDTIM:CL): 0b10 (3 cycles)
− Number of RAS precharge time cycles (SDTIM:TRP): 0b0000 (1 cycle)
− Number of latency cycles between RAS and CAS (SDTIM:TRCD): 0b0000 (1 cycle)
− Minimum number of row active time cycles (SDTIM:TRAS): 0b0000 (1 cycle)
RA: Row address
CA: Column address
Note:
− Perform the buffer register setting (SDTIM.BOFF) during SDON=0 of the SDRAM mode register.
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