CHAPTER 11: DSTC
530 FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E
In the transition state 2, if the DSTC does not execute any transfer, it immediately transits to the standby
state. But, if the DSTC executes a transfer, it transits to the standby state after that transfer has been
compulsorily ended.
If a transfer is ended by issuing a standby transition command, the DSTC writes 11 (compulsory end
code) to ST of the DES for that transfer to execute the DES close process. In addition, the EST bits in the
MONERS Register are set to 011. If the DSTC receives both HW transfer and SW transfer, it executes the
DES close processes for both transfers.
In addition, if the CPU issues a standby transition command to the DSTC, the DSTC executes the
following processes at the same time.
− The DSTC negates the SWINT interrupt signal and clears SWTR:SWST.
− The DSTC clears all HWINT[n] Registers and negates all HWINT[n] interrupt signals.
− The DSTC negates the ERINT interrupt signal.
− The DSTC sets all DQMSK[n] Registers to suppress the HW transfer request.
Though the issue of a standby transition command negates the ERINT interrupt signal, the values of the
MONERS Register remain unchanged. Therefore, if a transfer has been compulsorily stopped by a
standby transition command, the information of that transfer can still be checked by reading the MONERS
Register. In addition, the error record in the MONERS Register can be cleared only when the DSTC is in
the normal state. After a standby release command has made the DSTC return to the normal state, clear
the MONERS Register with the ERCLR command.
The initial values of all bits in the DQMSK[n] Register after a bus reset are 0. If a standby transition
command is issued, all bits in the DQMSK[n] are set to 1. To start an HW transfer after the DSTC has
returned to the normal state, clear the DQMSK[n] to be used for that HW transfer after finishing the setup
of a peripheral and rebuilding the DES.
Table 3-13 shows the accessibility of each control register in each state of the DSTC. "O" indicates that
register is accessible. "-" indicates that the access to that register is ignored by the DSTC and does not
function. "X" indicates that the process result becomes undefined depending on the change in the state of
the DSTC. It is prohibited to execute an access marked with "X".
In the standby state, transition state 1 and transition state 2, writing a value to SWTR:SWDESP cannot
start a new SW Transfer (the write access to the SWTR Register is ignored).
Table 3-13 Accessibility of Each Control Register in Each State of the DSTC
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