CHAPTER 11: DSTC
FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E 533
#21 The DSTC ends the transfer caused by the SW Start trigger in #1. The DSTC waits for either a new
Start Trigger or a succeeding Start Trigger. The DESP of the DES whose transfer has ended is kept in
SWTR:SWDESP.
#22 If that SW Start transfer has ended in the form of error and CFG:ESTE is 0, the DSTC proceeds to
#23. Otherwise the DSTC proceeds to #24.
#23 If there has been no error record in the MONERS Register, the MONERS Register records the error
information of the DES of the SW Start transfer that has caused an error. If there is an error record, the
DSTC sets the DER bit to 1. The DSTC clears SWTR:SWREQ to 0.
#24 The same process as #23 is executed. At the same time, the ESTOP bit in the MONERS Register is
set to 1, and the DSTC holds the start of the transfer of other HW Transfer.
#25 The transfer caused by the SW Start Trigger in #1 ends in the form of error. SWTR:SWST is not set
to 1 regardless of the value of CHRS. The DSTC waits for a new Start Trigger.
#26 In a write access to the SWTR Register from the CPU as explained in #1, if the condition in #2 is not
fulfilled, the DSTC ignores the write access to the SWTR Register. The DSTC does not accept the SW
Start request.
Additional Information on Controlling DSTC in SW Transfer
If the condition in #2 is not fulfilled, meaning that the SW Start transfer instruction has been executed
before #2, and that transfer has not ended (SWREQ ≠ 0) or the DSTC is not in the normal state (CMD ≠
00) or the DSTC is in the error stop state (ESTOP ≠ 0), the DSTC ignores the new SW Start request from
the CPU and does not accept it.
Pay attention to this behavior of the DSTC especially when using the DSTC with CFG:ESTE set to 1. If
the DSTC has stopped for an error due to another HW Transfer, any new SW Start request (write access
to a register) is ignored, and SWREQ is not set to 1. Therefore, if the DSTC reads 0 from the SWREQ bit
in the SWTR Register after making a write access to the SWTR Register, it cannot determine whether an
SW Start request has been ignored or a transfer has ended. Moreover, if using the DSTC with CFG:ESTE
set to 1, in an SW Transfer, set DES0:CHRS to a value that when the DSTC does not execute the Chain
Start, always sets SWTR:SWST to 1. With DES0:CHRS set in this way, after a write access has been
made to the SWTR Register, that both SWREQ bit and SWST bit read 0 indicates that no transfer request
has been accepted. If a transfer request has been accepted, since either SWREQ bit or SWST bit is 1,
the DSTC can determine whether an SW Start transfer has been ignored or a transfer has ended.
If the SWINT interrupt signal has been asserted by using the SWST bit, clear the SWST bit to 0 by issuing
an SWCLR command during interrupt processing. Even if the SWST bit is not cleared to 0, a new SW
Start request can be made by making a write access to the SWTR Register. However, in the process
explained in #3, the SWST bit is always cleared to 0 and the SWINT interrupt signal is negated.
In #4, if other HW Transfer is being executed or the Chain Start in that HW Transfer has been locked, it
may take time to start an SW Transfer even if it has a high priority.
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