CHAPTER 14: External Bus Interface
FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E 787
Power Down Mode Operation
When PDON bit of SDRAM mode register (SDMODE) is set to 1, the mode is transferred to Power down
mode if the access to SDRAM is not executed in the cycle (MADCLK) specified by Power down count
register (PWRDWN). In the refresh timing, the mode is returned again and the refresh is executed. If the
access is not executed in the period specified by Power down count register (PWRDWN) after refreshing,
the mode is transferred to the Power down mode again. To return, one cycle is required. When PDON bit
is set to 1 while SPON bit of SDRAM mode register (SDMODE) is 0, MSDCKE is set to L.
Figure 3-24 Power Down Mode Operation
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