CHAPTER 14: External Bus Interface
FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E 825
[bit15:0]REFC: Refresh Count
These bits set the interval of refresh operations.
The refresh operation starts when the specified cycle count (MSDCLK) elapses. When the writing is
executed during accessing, the executing access is aborted and the first refresh operation is
implemented to reflect the setting immediately.
Notes:
− The minimum refresh interval of REFC should not be shorter than cycle count (TREFC+1)
required for one-time refresh operation. Note that a hang-up would occur if the interval is set to
be shorter than the required cycle count.
− Set APBC2 bit of APB2 Prescaler Register (APBC2_PSR) so that the frequency of PCLK2
becomes the frequency of MSDCLK or below, when writing REFC bit in SDRAM operation. REFC
bit cannot set in SDRAM operation, when the division ratio of MSDCLK is 1/9 to 1/16 by using
MDIV bit of Division Clock Register (DCLKR).
− For the details of APB2 Prescaler Register, see 5.6. APB2 Prescaler Register of Chapter Clock.
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