CHAPTER 10: DMAC
FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E 493
[bit29] Reserved: Reserved bit
"0" is read out from this bit.
When writing this bit, set it to "0".
[bit28] PR : Priority Rotation
This bit controls the order of transfer priority among channels.
When this bit is set to "0", the priority order is fixed for all of the channels.
When this bit is set to "1", the priority order is determined in a rotation method for all of the channels.
Fixes the priority order.
(ch.0>ch.1>ch.2>ch.3>ch.4>ch.5>ch.6>ch.7) (Initial value)
Applies the rotation method to the priority order.
For selection of the transfer priority order, see Section "3.5 Channel Priority Control".
[bit27:24] DH : DMA Halt (All-channel pause bit)
This bit controls the pause/cancellation of transfer operations for all of the channels.
When this bit is set to a value other than "0000", all of the channels that are currently performing a
transfer are put on pause. When it is set to "0000", the transfers are resumed.
Even if a transfer request from an external/peripheral device is asserted, the channels in Pause state
ignore the transfer request. In the cases of Block transfer and Burst transfer, the relevant channel does
not start a transfer, even if the pause is cleared. In order to complete a transfer when a pause is set
during the transfer, an additional transfer request is required after the pause is cancelled.
This bit can be used to put a transfer on pause without resetting the configuration registers of all of the
channels.
Cancels the pause of transfers for all of the channels. (Initial value)
Puts the transfers of all of the channels on pause.
[bit23:0] Reserved: Reserved bits
"0" is read out from these bits.
When writing these bits, set them to "0".
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