Cypress FM4 Series - Page 562

CHAPTER 11: DSTC
562 FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E
HWDESP[n] Register has been modified, write "1" to the RBDIS bit. If the RBDIS bit is set to "1", the
DSTC does not use the read skip buffer function or the HWDESPBUF function, but it operates referring to
the DES value on the memory and the value of the HWDESP[n] Register. After the DSTC has executed
processes with updated values of the DES and the HWDESP[n] Register, the buffer function can be
enabled again by writing "0" to the RBDIS Register.
bit[11] ESTE (Error stop enable)
Access
Function
Writing "0"
The DSTC does not enter the error stop state even when a transfer error occurs. (Initial value)
If there is another transfer request, the DSTC starts the transfer for that request.
Writing "1"
The DSTC enters the error stop state when a transfer error occurs.
If there is another transfer request, the DSTC holds the start of the transfer for that request.
Reading
A read access to this bit reads the value of this bit.
bit[12:14] SWPR[2:0] (Software transfer priority)
In the arbitration of Arbiter 2, if the SW transfer request conflicts with the HW transfer request, Arbiter 2
specifies the probability of the SW transfer acquiring the transfer right. The value of the SWPR bits can be
modified even when the DSTC is executing a transfer. After the value of the SWPR bits in the CFG
Register has been modified, it is applied from the next SW Start Trigger.
Access
Function
Writing "000"
Sets the priority of the SW transfer to the highest priority.
(If an SW transfer request is made while an HW transfer is in progress, the SW transfer starts after
the HW transfer has ended.)
Writing "001"
Sets the probability of the SW transfer acquiring the transfer right to 1/2.
Writing "010"
Sets the probability of the SW transfer acquiring the transfer right to 1/3.
Writing "011"
Sets the probability of the SW transfer acquiring the transfer right to 1/7.
Writing "100"
Sets the probability of the SW transfer acquiring the transfer right to 1/15. (Initial value)
Writing "101"
Sets the probability of the SW transfer acquiring the transfer right to 1/31.
Writing "110"
Sets the probability of the SW transfer acquiring the transfer right to 1/63.
Writing "111"
Sets the priority of the SW transfer to the lowest priority.
(The SW transfer starts only when there is no HW transfer request.)
Reading
A read access to these bits reads the value of these bits.
bit[15] Reserved
Write "0" in a write access to this bit. In a read access to this bit, "0" is read out.