CHAPTER 14: External Bus Interface
FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E 835
− When you want to output the division clock, clock output setup is required with the use of GPIO.
See a separate chapter I/O Port for the details of the setups.
To output the MCLKOUT set MCLKON=1. To output MSDCLK, set SDRAM mode register
(SDMODE) to MSDCLKOFF=0.
− When MCLKOUT is set to output by dividing the frequency by one, set MCLKON=1, and
MDIV=0000.
When MSDCLK is set to output by dividing the frequency by one, set SDRAM mode register to
MSDCLK=1 and MDIV=0000.
In this case, check External bus clock output Characteristics in Data sheet.
− To change the division ratio, make sure to set MCLKON=0 and SDRAM mode register
(SDMODE) to MSDCLKOFF=1 before change the MDIV.
Also, after changing the MDIV, read the registers to check that the clock division ratio was
changed.
− Any change to this register during external bus accessing is prohibited.
− Cannot set REFC bit of Refresh Timer Register (REFTIM) in SDRAM operation and SDRAM
Command Register (SDCMD), when the division ratio of MSDCLK is 1/9 to 1/16.
(MDIV=0b1000~0b1111).
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