CHAPTER 10: DMAC
FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E 475
At the beginning, three channels, namely ch.0, ch.1 and ch.2, perform their transfer operations in
Block transfer mode. ch.2 successfully completes its transfer, moves to Disable state and sets
SS[2:0]=101. Then, ch.0 and ch.1 perform transfers alternately.
If an instruction to put all-channel operation on pause is issued from CPU at this point, the
following operation applies. As ch.0 is subject to the Transfer Gap timing, it immediately moves to
Pause state and sets SS[2:0]=111. As ch.1 is in the middle of transfer operation, it performs the
transfer until the timing of the next Transfer Gap, and then moves to Pause state and sets
SS[2:0]=111. As ch.2 is in Disable state, it remains in the Disable state without changing SS. DS
is set, when all of the channels stop their operations.
Next, if an instruction to enable all-channel operation (instruction to cancel the pause) is issued
from CPU, the following operation applies. ch.0 and ch.1 return to Transfer state and clear
SS[2:0] to "000". As ch.2 is in Disable state (DE=1, EB=0), it remains in that state without starting
the operation. Because the pause of all of the channels has been cancelled now, DS is reset.
11. Operation in Disable state
A channel in Disable state remains in the Disable state, unless the conditions such as DE=1,
DH=0000, EB=1, and PB=0 are established. Although in 1-2 of the software procedure, DE is set
from the conditions of DE=0 and EB=0, and then, EB is set, there is no problem to set EB before
DE. DE can be set last after all of the transfer settings of multiple channels subject to transfer are
completed. In this case, an instruction can be issued to allow the multiple channels subject to
transfer to start their transfer operations simultaneously. If such instruction for simultaneous start
of transfers is issued, DMAC selects the channels to which transfers are to be started, according
to the PR setting (PR can be set or changed, only when all-channel operation is disabled).
If an instruction to disable individual-channel operation, an instruction to put individual-channel
operation on pause, an instruction to disable all-channel operation or an instruction to put
all-channel operation on pause is issued to a channel in Disable state, only the settings of DE, DH,
EB and PB are changed, but the conditions of DE=1, DH=0000, EB=1 and PB=0 are not
established. Therefore, the relevant channels do nothing and do not change SS[2:0]. If an
instruction to put all-channel operation on pause is issued from CPU to a channel in Disable state,
as shown in the example of ch.2 operation in Figure 4-3, that channel does not change its state
with SS[2:0] indicating the completion of the previous transfer.
If an instruction to put individual- or all-channel operation on pause is issued to a channel in
Disable state, it may be put in Disable state with DE=1, EB=1, (DH!=0000 or PB=1). Although the
bit values in this state are the same as DE, EB, DH and PB, they can be distinguished because
SS[2:0] has a different value. Figure 4-4 shows such an example.
Figure 4-4 Example of Operation when Instruction to Put Individual-channel Operation on Pause is Issued in
Disabled State
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