CHAPTER 10: DMAC
474 FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E
Even if instructed from CPU, the transfer may not be put on pause, and instead, it may be
successfully completed due to factors such as transfer mode (Burst/Block/Demand) and transfer
status (the number of transfers performed, the timing of instruction to put the operation on pause).
Also, if a transfer error occurs before the transfer stops, error stop applies to the transfer.
Figure 4-3 Operation when All-channel Pause is Instructed
9. Pause state
SS is read from CPU to confirm the pause of the transfer. The SS of a channel in Pause state is
111. While in this state, it cannot be cleared from CPU.
Even during the pause, the transfer content cannot be specified or changed (rewriting DMACSA,
DMACDA, DMACA[29:0] or DMACB[31:1]). Also, when a channel in Pause state is instructed to
pause, it continues to remain in the Pause state.
10. Pause state / Cancellation of transfer pause
If an instruction to enable individual-channel operation is issued to a channel that has been in
Pause state due to an instruction to put individual-channel operation on pause, that channel
returns to Transfer state. If an instruction to enable all-channel operation is issued to channels
that have been in Pause state due to an instruction to put all-channel operation on pause, those
channels return to Transfer state. If both of the pause instructions have been given, issue an
instruction to cancel both of them.
After the instruction, SS[2:0] is cleared to 000 via DMAC.
If an instruction to enable individual-channel operation and an instruction to enable all-channel
operation are issued in Pause state, they instruct the pause to be cancelled. If they are issued in
Disable state, attention must be paid, as they may instruct a new transfer to be started. See Step
11 in the software procedure.
Figure 4-3 shows an example of the case where an instruction to put all-channel operation on
pause. The explanation of the figure is as follows.
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