CHAPTER 10: DMAC
FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E 473
6. Transfer state, Pause state => Disable state / Forced transfer stop
If an instruction to disable individual-channel operation or an instruction to disable all-channel
operation is issued from CPU to a channel in Transfer state or Pause state, the transfer operation of
that channel can be forced to stop (for the operation when an instruction to disable operation is
issued to a channel in Disable state, see Step 11 in the software procedure).
If an instruction is given from CPU, the relevant channel suspends its transfer process. It clears EB,
PB and ST and moves to Disable state. It sets SS[2:0]=010 and gives the notification that the
transfer of that channel has been forced to stop. If unsuccessful transfer completion interrupt has
been enabled by EI, an interrupt occurs. BC, TC, DMACSA and DMACDA to which reload has not
been specified hold the values set at the time of the transfer suspension.
After instructed from CPU, the transfer stops at the timing when the relevant channel is not
performing transfer (in Transfer Gap before the transfer starts), as shown in the Example 3 in Figure
4-2. In the case of a channel in Pause state, the transfer stops immediately. There is a time
difference (Transition state) between the instruction and the stop. It may take some time, depending
on the BC setting. As a new transfer cannot be set or started during this period, always make sure
that the operation has stopped before setting the next transfer.
In the case of an instruction to disable all-channel operation, the timing to stop varies depending on
the channel. As DS is set when all of the channels are stopped, it can confirm that all of the
channels have stopped.
Even if instructed from CPU, the transfer may not be forced to stop, and instead, it may be
successfully completed due to factors such as transfer mode (Burst/Block/Demand) and transfer
status (the number of transfers performed, the timing of instruction to disable the operation). Also, if
a transfer error occurs before the transfer stops, error stop applies to the transfer.
7. Disable state / Post-transfer process
SS is read from CPU to check the state of completion of the transfer. CPU clears SS to prepare for
the next transfer. If interrupts have been enabled, the interrupt signal from DMAC is deasserted by
clearing SS.
In the case of successful completion, CPU resets the transfer content, as required. If each reload
has been specified, the values set before the start of the transfer are reloaded to BC, TC, DMACSA
and DMACDA. If each reload has not been specified, BC and TC are initialized to 0. DMACSA and
DMACDA show the address for the next transfer.
In the cases of error stop and forced stop, BC, TC, DMACSA and DMACDA must always be reset,
because they may have the values set at the time of the suspension.
If the transfer is stopped due to an instruction to disable all-channel operation, DE is set to 0;
therefore, the next transfer will require an instruction to enable all-channel operation and an
instruction to enable individual-channel operation.
8. Transfer state / Transfer pause
If an instruction to put individual-channel operation on pause or an instruction to put all-channel
operation on pause is issued from CPU to a channel in Transfer state, the transfer operation of the
relevant channel(s) can be put on pause (for the operation when an instruction to put the operation
on pause is issued to a channel in Disable state, see Step 11 in the software procedure).
If an instruction is given from CPU, the relevant channel(s) temporarily suspends the transfer
process. It sets SS=111 and gives the notification that it is in Pause state. In this case, no interrupt
can be generated.
After instructed from CPU, the transfer stops at the timing when the relevant channel is not
performing transfer (in Transfer Gap before the start of the transfer). There is a time difference
(Transition state) between the instruction and the stop. It may take some time, depending on the BC
setting. See Figure 4-3.
In the case of an instruction to put all-channel operation on pause, the timing to stop varies
depending on the channel. As DS is set when all of the channels are stopped, it can confirm that all
of the channels have stopped. See Figure 4-3.
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