CHAPTER 10: DMAC
472 FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E
Figure 4-2 Example of Operation of Software-Block Transfer
DMA status Transfer
Example of Block transfer mode (software DMA operation)
start / normal end / error stop / force stop
Transfer action
Disable
Example 1 :normal end
Disable
TC(no reload) 3 2 1 0
SS 000
101 (normal end)
Start request from CPU
Transfer normal end
BC
Transfer
Example 2 : error stop
Disable
3 2
000 011 (Source access error )
Transfer
Example 3 : enforced stop from CPU
Disable
3 2
000 010 (Stop request)
DMA status
Transfer action
Disable
TC(no reload)
SS
BC
DMA status
Transfer action
Disable
TC(no reload)
SS
BC
Transition state
Start request from CPU Transfer error stop
Start request from CPU
Stop request from CPU
Transfer enforced stop
5. Transfer state => Disable state / Transfer error stop
The channel in Transfer state suspends the transfer process, if an address overflow, transfer
source access error or transfer destination access error occurs. It clears EB, PB and ST and
moves to Disable state. It sets the value that indicates the error content to SS[2:0] to give the
notification of the error stop. See Example 2 in Figure 4-2. If unsuccessful transfer completion
interrupt has been enabled by EI, an interrupt occurs. BC, TC, DMACSA and DMACDA to which
reload has not been specified hold the values set at the time of the transfer suspension.
Normally, a transfer error occurs, when an attempt is made to access an address area that does
not exist in the system bus or an address area that prohibits access from DMAC. No such error
occurs in general applications.
To Next Page
Loading...
