CHAPTER 10: DMAC
FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E 471
Description of Each State
Disable state
In this state, the transfer of the channel to be controlled is prohibited. Channels in this state do
nothing and wait for instruction from CPU. At the system reset, DE=0, EB=0, DH=0000 and PB=0
apply to this Disable state.
Transfer state
In this state, the transfer of the channel to be controlled is enabled. Channels in this state perform
transfer operation as specified. Once all of the transfer operations are completed, they return to
the Disable state. The state is also changed as instructed by CPU.
Pause state
In this state, the channel to be controlled has its transfer operation on pause due to an instruction
to pause, issued by CPU, and is waiting for another instruction from CPU.
Explanation of Control Procedure
1. Disable state / Preparation for transfer
Specify via CPU the transfer content for the channel to be controlled (writing to DMACSA,
DMACDA, DMACA and DMACB). For details of transfer content to be specified, see “5. Registers
of DMAC”. When generating an interrupt from DMAC upon the completion of transfer, set EI and
CI.
The following restrictions apply to software transfer. Specify ST=1 and IS[5:0]=000000. Demand
transfer mode cannot be specified to MS. Always set "0" to EM.
Give an instruction to enable all-channel operation and set PR. Data can also be written to
DMACA at the same time in Step 2.
2. Disable state => Transfer state / Start of transfer
Give an instruction to enable individual-channel operation from CPU. When DE=1, EB=1,
DH=0000 and PB=0 are set, the channel to be controlled moves to Transfer state.
3. Transfer state
When the channel in Transfer state becomes enabled to access the system bus, it performs a
transfer according to the transfer content (it may take time to start the transfer, depending on the
status of other channels). In the case of Block transfer, a Transfer Gap is generated every time
TC is updated. In the case of Burst transfer, no Transfer Gap is generated. During the transfer
operation, BC, TC, DMACSA and DMACDA indicate the remaining number of transfers and the
transfer address at that time point. The transfer status can be checked by reading from CPU.
The specified transfer content cannot be changed via CPU to the channel in Transfer state
(rewriting to DMACSA, DMACDA, DMACA[29:0], DMACB[31:1]). (However, EB, PB and EM can
be rewritten.)
4. Transfer state => Disable state / Successful completion of transfer
When transfers are successfully completed for the number of times calculated by (BC+1)×
(TC+1), the channel in Transfer state clears EB, PB and ST and moves to Disable state. It sets
SS=101 to provide the notification of the successful completion. See Example 1 in Figure 4-2. If
successful transfer completion interrupt has been enabled by CI, an interrupt occurs. If reload has
been specified to BC, TC, DMACSA and DMACDA, such reload is executed according to the
specified transfer content.
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