CHAPTER 10: DMAC
478 FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E
Description of Each State
Disable state
See Explanation of Control Procedure in "4.2 DMAC Operation and Control Procedure for
Software Transfer".
Wait-1st-trigger state
In this state, the channel to be controlled is enabled to perform transfer. A channel in this state
waits for the first transfer request from a Peripheral to be asserted. It also changes its state upon
instruction from CPU.
Transfer state
In this state, the channel to be controlled has received the first transfer request from the
Peripheral. A channel in this state performs transfer operation as specified. Once all the transfer
operation is completed, it returns to Disable state. It also changes its state upon instruction from
CPU.
Pause state
See Explanation of Control Procedure in "4.2 DMAC Operation and Control Procedure for
Software Transfer".
Explanation of Control Procedure
1. Disable state / Preparation for transfer
See Step 1 in the software transfer procedure.
The following restrictions apply to hardware transfer.
Decide in advance on which Peripheral’s interrupt signal to be used as the transfer request signal
to DMAC using the interrupt controller block (See 4.1 DMA Request Selection Register
(DRQSEL) in Chapter Interrupt.). Set ST=0 and specify which Peripheral’s transfer request to be
processed at the channel that will perform the transfer, by IS at the same time. Multiple channels
cannot process transfer request of the same Peripheral. In the case of Demand transfer mode,
set BC=0. This section explains the operation when EM=0 is set.
2. Disable state => Wait-1st-trigger state / Transfer enabled
An instruction to enable individual-channel operation is issued from CPU. When DE=1, EB=1,
DH=0000 and PB=0 are set, the channel to be controlled moves to Wait-1st-trigger state.
3. Wait-1st-trigger state / Start of transfer
The channel in Wait-1st-trigger state is waiting for the transfer request signal to be asserted from
the Peripheral or for an instruction from CPU. When the first transfer request signal is asserted, it
moves to Transfer state.
4. Transfer state
See Step 3 in the software transfer procedure.
In the case of hardware transfer, a channel in Transfer state performs transfer operation by the
transfer request signal from a Peripheral, as described in Sections 3.3 Hardware-Demand
Transfer and 3.4 Hardware-Block Transfer & Burst Transfer. In each mode, match the number of
transfer requests from the Peripheral with the number of transfer requests required by DMAC.
Below is the explanation for the operation when the number of transfer requests goes over or
below the requirement in each operation mode.
Figure 4-6 shows a case of Demand transfer. In the case of Demand transfer, the number of
transfer requests required to complete the transfer is TC+1. Unless the number of transfer
requests goes over or below the requirement, CPU does not have to intervene (Example 1 in
Figure 4-6).
If the number of transfer requests generated from the Peripheral exceeds the DMAC’s setting for
the number of transfers, DMAC moves to Disable state after the completion of the specified
number of transfers. In the Disable state, no further transfers are executed. Also, as the
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