Cypress FM4 Series - Page 479

CHAPTER 10: DMAC
FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E 479
excessive transfer request signals are not cleared from DMAC, the asserted state continues
(Example 2 in Figure 4-6).
If the number of transfer requests generated from the Peripheral is smaller than DMAC’s setting
for the number of transfers, DMAC waits for the remaining number of transfer requests in Transfer
state (Example 3 in Figure 4-6).
It is supposed that DMAC’s transfer processing may be too slow to catch up with the generation
interval of transfer requests from Peripheral. In the case of Demand transfer, the transfer request
signal remains asserted; therefore, as many as TC+1 of transfers can be performed (Example 4
in Figure 4-6).
Figure 4-6 Operation of Hardware-Demand Transfer
Example 1: (TC+1)== Transfer request from Peripheral
Disable
Wait 1st
trigger
Transfer Disable
2012
000 101 (normal end)
normal end
Disable
Wait 1st
trigger
Transfer Disable
1st Transfer request
from Peripheral
Transfer request
Transfer action
SS
Start request from CPU
Example 2: (TC+1) < Transfer request from Peripheral
DMA status
TC (reload)
Transfer request
Transfer action
SS
TC (reload) 2012
000
101 (normal end)
Example 3: (TC+1) > Transfer request from Peripheral
Disable
Wait 1st
trigger
Transfer
DMA status
Transfer request
Transfer action
SS
TC (reload)
012
Example 4: DMA transfer be delayed
DMA status
Transfer request
Transfer action
SS
TC (reload)
Disable
Wait 1st
trigger
Transfer Disable
012
000 101 (normal end)