Cypress FM4 Series - Page 480

CHAPTER 10: DMAC
480 FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E
Figure 4-7 shows a case of Block transfer. In the case of Block transfer, the number of transfer
requests required to complete the transfer is TC+1. Unless the number of transfer requests goes
over or below the requirement, CPU does not have to intervene (Example 1 in Figure 4-7).
Figure 4-7 Operation of Hardware-Block Transfer
DMA status
Transfer
Block transfer mode (hardware DMA operation)
Transfer action
Example1: (TC+1)== Transfer request from Peripheral
TC(reload) 2 1 0
SS 000 101
Start request from CPU Normal end
Wait
Transfer request
1st Transfer request
from Peripheral
2
DMA status
Transfer action
Example2: (TC+1) < Transfer request from Peripheral
TC(reload)
SS
Transfer request
Example3: (TC+1) > Transfer request from Peripheral
Example4: DMA transfer be delayed
Transfer
2 1 0
000 101
Wait
2
Disable
Disable
Disable
Disable
DMA status
Transfer action
TC(reload)
SS
Transfer request
Transfer
2 1 0
000
Wait
Disable
DMA status
Transfer action
TC(reload)
SS
Transfer request
Transfer
2 1 0
000
Wait
Disable
If the number of transfer requests generated from the Peripheral exceeds the DMAC’s setting for
the number of transfers, DMAC moves to Disable state after the completion of the specified
number of transfers. In the Disable state, no further transfers are executed. Also, as the