CHAPTER 10: DMAC
FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E 481
excessive transfer request signals are not cleared from DMAC, the asserted state continues, In
this case, deassert the transfer request signal from CPU (Example 2 in Figure 4-7).
If the number of transfer requests generated from the Peripheral is smaller than DMAC’s setting
for the number of transfers, DMAC waits for the remaining number of transfer requests in Transfer
state (Example 3 in Figure 4-7).
It is supposed that DMAC’s transfer processing may be too slow to catch up with the generation
interval of transfer requests from Peripheral. In the case of Block transfer, if DMAC’s transfer
processing is delayed from the transfer request from the Peripheral, the rising edge of the next
transfer request signal during the transfer operation is ignored. Also, the transfer request signal
asserted during the transfer operation is cleared from DMAC. Then, DMAC waits for the
remaining transfer requests in Transfer state (Example 4 in Figure 4-7).
In the case of Burst transfer, all of the (BC+1)×(TC+1) of transfers are performed when it
becomes accessible to the system bus after the first transfer request is received. The required
number of transfer requests from the Peripheral is only the first one. If the number of transfer
request signals generated exceeds the requirement, it is ignored in Disable state, just like Block
transfer.
5. Transfer state => Disable state / Successful completion of transfer
See Step 4 in the software transfer procedure.
6. Transfer state => Disable state / Transfer error stop
See Step 5 in the software transfer procedure.
7. Transfer state => Disable state / End of Peripheral stop request
The channel in Transfer state suspends its transfer processing, if the transfer stop request signal
is asserted from the Peripheral. It clears EB, PB and ST and moves to Disable state. It sets "010"
to SS[2:0] and gives the notification of the error stop. If interrupts have been enabled by EI, an
unsuccessful transfer completion interrupt occurs. BC, TC, DMACSA and DMACDA to which
reload has not been specified hold the values set during the suspension of the transfer. Attention
must be paid to the SS[2:0] value, which is the same as the stop request from software.
8. Transfer state, Pause state => Disable state / Forced termination of transfer
See Step 6 in the software transfer procedure.
9. Disable state / Post-transfer processing
See Step 7 in the software transfer procedure.
Normally, in the cases of stop request from Peripherals, forced termination from software and
transfer error stop, the transfer request signal remains asserted, because the number of transfers
processed is smaller than the number of transfer requests from the Peripheral. Instruct from CPU
the Peripheral to deassert the transfer request signal. In the case of stop request from
Peripherals, the transfer request signal is masked as long as the stop request signal is asserted.
Also deassert the transfer stop request signal.
Even if DMAC has successfully completed the specified number of transfers, the transfer request
signal may remain asserted or may be reasserted, depending on Peripheral’s settings. Attention
must be paid to the possibility that this may affect the next transfer.
10. Transfer state, Pause state / Transfer pause
See Step 8 in the software transfer procedure.
11. Pause state
See Step 9 in the software transfer procedure.
The channel in Pause state does not execute transfer, even if the transfer request signal from the
Peripheral is asserted. It does not clear the transfer request signal either.
12. Pause state / Cancellation of transfer pause
See Step 10 in the software transfer procedure.
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