CHAPTER 10: DMAC
482 FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E
When an instruction to cancel the pause is issued while it is in Pause state, it returns to Transfer
state. If the transfer request signal was asserted in the previous Pause state, the operation to
follow varies as shown below, depending on the transfer mode.
In the case of Demand transfer mode, the transfer request signal remains asserted from the
Pause state. Therefore, the transfer is resumed when DMAC returns to Transfer state, and the
transfer request signal is cleared as normal. See Figure 4-8.
Figure 4-8 Operation of Demand Transfer in Pause State
DMA status
Transfer request
Pause Transfer
Transfer action
Transfer
DMA status
Transfer request
Pause
Transfer
Transfer action
Transfer
Case of transfer request be asserted during pause state
Case of no transfer request be asserted during pause state
In the case of Block transfer mode, the transfer request signal remains asserted. Even when it
returns to Transfer state, the rising edge of the transfer request signal is not detected, and the
transfer is not resumed. Therefore, the transfer request is ignored during Pause state. Also, the
transfer request signal is not cleared from DMAC. To resume the transfer which has been put on
pause, instruct from CPU the Peripheral to deassert the transfer request signal after an
instruction to cancel the pause is issued to DMAC. After that, the transfer will be resumed when
the next transfer request is generated from the Peripheral. In this case, attention must be paid to
the difference between the number of transfer requests output from the Peripheral and the
number of transfer requests received by DMAC. See Figure 4-9.
Figure 4-9 Operation of Block Transfer in Pause State
DMA status
Transfer request
Pause Transfer
Transfer action
Transfer
DMA status
Transfer request
Pause
Transfer
Transfer action
Transfer
Case of transfer request be asserted during pause state
De-assert from CPU
Case of no transfer request be asserted during pause state
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