CHAPTER 10: DMAC
FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E 483
13. Operation in Disable state and Wait-1st-trigger state
See Step 11 in the software transfer procedure.
If the transfer request signal is not asserted to the channel in Disable state, the specifications of
the transfer content can be changed freely (rewriting to registers DMACSA, DMACDA,
DMACA[29:0], and DMACB).
If the transfer request signal is asserted or may be asserted to the channel in Disable state, the
specifications of IS, ST and MS in the transfer content cannot be changed. If an attempt is made
to change these settings, DMAC may perform unexpected behaviors. To change the settings of IS,
ST and MS, first clear the transfer request signal to both of the Peripherals (used before and after
the change) from CPU, and then always change the settings while the transfer request signal is
deasserted. See Figure 4-10.
Figure 4-10 Changing IS, ST and MS Settings
The specifications of the transfer content cannot be changed to the channel in Wait-1st-trigger
state from CPU
If the transfer request signal is not asserted to the channel in Wait-1st-trigger state, it moves to
Disable state when CPU issues an instruction to disable individual- or all-channel operation or an
instruction to put individual- or all-channel operation on pause. In this case, it is considered that
the enabled transfer has been cancelled. In any case, SS does not change.
If the transfer request signal may possibly be asserted to the channel in Wait-1st-trigger state, it
should be noted that DMAC has already started or completed the transfer before the attempted
cancellation of the enabled transfer from CPU.
In Disable state, DMAC does not start the transfer or clear the transfer request, even if the
transfer request signal is asserted. If it moves to Wait-1st-trigger state by instruction from CPU
while the transfer request signal is asserted, the following operation applies (only when the
settings of IS, ST and MS are not intended to be changed, as explained earlier).
In the case of Demand transfer mode, DMAC immediately moves to Transfer state and starts the
transfer, because the transfer request signal remains asserted. The transfer request signal is
cleared from DMAC as normal. See Figure 4-11.
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