Cypress FM4 Series - Page 484

CHAPTER 10: DMAC
484 FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E
Figure 4-11 Operation of Demand Transfer in Disable State
DMA status
Transfer request
Wait 1st
trigger
Transfer
Transfer action
Disable
DMA status
Transfer request
Transfer
Transfer action
Disable
Case of transfer request be asserted during disable state
Case of no transfer request be asserted during disable state
Wait 1st
trigger
In the case of Block transfer mode, the transfer request signal remains asserted. Even when it
moves to Wait-1st-trigger state, the rising edge of the transfer request signal is not detected, and
the transfer is not resumed. Therefore, the transfer request is ignored during Disable state. Also,
the transfer request signal is not cleared from DMAC. To resume the transfer, instruct DMAC to
move to Wait-1st-trigger state, and then instruct from CPU the Peripheral to deassert the transfer
request signal. After that, it will move to Transfer state and the transfer will be resumed when the
next transfer request is generated from the Peripheral. In this case, attention must be paid to the
difference between the number of transfer requests output from the Peripheral and the number of
transfer requests received by DMAC. See Figure 4-12.
Figure 4-12 Operation of Block Transfer in Disable State
DMA status
Transfer request
Transfer
Transfer action
DMA status
Transfer request
Wait 1st trigger
Transfer
Transfer action
Disable
Case of transfer request be asserted during disable state
De-assert from CPU
Case of no transfer request be asserted during disable state
Wait 1st
trigger
Disable