CHAPTER 2-2: Clock Gating
FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E 111
A/D Converter
A/D Timer Trigger Selection
When the base timer is used as a startup trigger of the A/D converter, set the operation clock of the
selected base timer channel to the supply side.
GPIO
Restrictions when bus clock is gated
While the bus clock of GPIO is gated, some functions of I/O port cannot be used as shown in Table 5-3.
Be sure to confirm the using conditions and execute the bus clock control of GPIO.
For details on I/O port functions, see Chapter I/O Port.
Table 5-3 Restrictions When GPIO Clock is Gated
GPIO Function-Input level reading
(PDIR register reading)
GPIO Function-Output Level Switching and Status Confirmation
(PDOR register reading/writing)
I/O port Mode Switching
(Setting change of PFR, PCR, DDR, ADE, SPSR, EPFR, and PZR
registers)
Peripheral Function Operation (Signal Input and Output)
External Interrupt/NMI Control
Return from Deep Standby Mode
(WKUP pin input)
*: Available: can be used, Prohibited: cannot be used.
I
2
S Interface
Clock control target
The gating and supplying of the clock for the I
2
S cannot be controlled with I2SCK bit of the peripheral
clock control register 2 (CKEN2). Execute the control of the clock for the I
2
S with I2SEN bit of I
2
S clock
control register (ICCR). For details, see I
2
S Clock Generation in FM4 Family Peripheral Manual
Communication Macro Part.
HDMI-CEC/Remote Control Reception
Clock control target
The gating and supplying of the sub clock for the HDMI-CEC/Remote Control Reception cannot be
controlled with CECCK bit of the peripheral clock control register 2 (CKEN2). Execute the control of the
sub clock for the HDMI-CEC/Remote Control Reception with CECCKE bit of sub clock control register
(RCK_CTL). For details, see Chapter Low Power Consumption Mode.
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