CHAPTER 6: Low Power Consumption Mode
208 FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E
Return from Timer Mode
The CPU returns from Timer mode in one of the following situations.
Return due to reset
If a reset (INITX pin input reset, low voltage detection reset, hardware watchdog reset, clock supervisor
reset or anomalous frequency detection reset (main timer mode or PLL timer mode)) occurs, the CPU
switches to high speed CR run mode regardless of the clock mode.
In Timer mode, since the software watchdog reset is not available, it cannot be used to make the CPU
return from Timer mode.
Return due to interrupt
On receiving a request for an effective interrupt, which can be an NMI interrupt, an external interrupt, a
hardware watchdog timer interrupt, a USB wakeup interrupt, a watch counter interrupt, an RTC interrupt,
a HDMI-CEC/ Remote Control Reception interrupt, a low voltage detection interrupt a GDC interrupt, in
Timer mode, the CPU returns from Timer mode and transits to a Run mode corresponding to the clock
mode indicated in the RCM[2:0] bits in the System Clock Mode Status Register (SCM_STR).
Table 3-6 Operation Mode after Return from Timer Mode due to Interrupt
Oscillation stabilization wait at return
On returning from Timer mode due to a reset, the CPU waits for the stabilization of high speed CR clock
oscillation and that of low speed CR clock oscillation. In the case of returning from Timer mode due to an
interrupt, the CPU does not have to wait for the oscillation to stabilize.
Built-in regulator voltage stabilization wait at return
The CPU automatically secures a voltage stabilization wait time (a few hundred µs) for the operation
mode transition of the built-in regulator before returning from low speed CR timer mode or sub timer
mode due to a reset or an interrupt. After the voltage stabilization wait time has lapsed, the CPU executes
the return operation.
Notes:
− If the priority of an interrupt used for making the CPU return from Timer mode is not set to a level
for making the CPU return from Timer mode, after an interrupt has been generated, the clock
returns from Timer mode, but the CPU does not return from Timer mode and continues stopping.
Therefore, always set the priority of an interrupt used for making the CPU return from Timer
mode to a level that can make the CPU return from Timer mode.
− Before making the CPU transit to Timer mode, ensure that no factor for returning from Timer
mode shown in Table 3-4 has been set. ( include the interrupt pending register in the NVIC) If
such factor has been set, clear that factor.
− If the CPU transits to Timer mode during debugging, as the clock supply to the CPU stops, the
CPU cannot return to a RUN mode by using the ICE. Use a reset or an interrupt to make the CPU
return to a Run mode.
− Before making the CPU transit to low speed CR timer mode or sub timer mode, ensure that the
Flash memory automatic algorithm has terminated.
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