Cypress FM4 Series - Page 499

CHAPTER 10: DMAC
FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E 499
[bit18:16] SS[2:0] : Stop Status (stop status notification)
These bits represent a code that indicates the stop status or completion status of a transfer.
The following table shows the available codes.
If a successful transfer completion interrupt or unsuccessful transfer completion interrupt is issued, the
interrupt signal is deasserted by writing "000" to these bits.
bit18:16
Description
000
Initial value
001
Termination by transfer error (address overflow)
010
Termination by transfer stop request (stop by transfer stop request for Peripheral or the
disabling of transfer by the EB/DE bit)
011
Termination by transfer error (transfer source access error)
100
Termination by transfer error (transfer destination access error)
101
Successful transfer completion
110
Reserved
111
Transfer on pause
If various errors occur simultaneously, the termination code is indicated according to the following priority.
Highest priority
Reset
Clearing by writing "000"
Address overflow
Stop request
Transfer source access error
Transfer destination access error
Lowest priority
[bit15:1] Reserved: Reserved bits
"0" is read out from these bits.
When writing these bits, set them to "0".
[bit0] EM : Enable bit Mask (EB bit clear mask)
This bit is used to mask the clear of the EB bit (DMACA[31]) from DMAC upon completion of the transfer.
In the case of EM=0, DMAC clears the EB bit (DMACA[31]) to "0" upon completion of the transfer.
In the case of EM=1, it does not clear the EB bit upon completion of the transfer. This function allows
transfers to be repeated without instruction from CPU.
This function can only be used for hardware transfer. To use the function, enable the reload function of
RC, RS and RD bits.
bit
Function
0
Clears DMACA:EB to 0 upon completion of the transfer. (Initial value)
1
Does not clear DMACA:EB upon completion of the transfer.